Features
•
Third Generation Programmable Logic Structure
•
•
•
•
•
•
•
•
•
– Easily Achieves Gate Utilization Factors of 80 Percent
Increased Logic Flexibility
– 86 Inputs and 72 Sum Terms
Flexible Output Macrocell
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
High-Speed
Low-Power — Less than 0.5 mA Typical (ATV2500L)
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Asynchronous Clocks and Resets
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
Proven and Reliable High Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
40-pin Dual-In-line and 44-Lead Surface Mount Packages
High-Density
UV-Erasable
Programmable
Logic Device
ATV2500H
ATV2500L
Block Diagram
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
Pin Configurations
Pin Name
IN
I/O
I/O, 0,2,4..
I/O, 1,3,5..
*
VCC
Function
Logic Inputs
Bidirectional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
No Internal Connection
+5V Supply
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC
I/O1
I/O0
*
IN
IN
IN
IN
IN
IN
IN
I/O06
* = No Connect
Rev. 0025E–05/98
I/O12
IN
IN
IN
IN
IN
IN
IN
*
I/O18
I/O19
18
19
20
21
22
23
24
25
26
27
28
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
1
There are 416 product terms available. Four product terms
are input to each sum term. The three sum terms per logic
cell can be combined to provide up to twelve product terms,
combinatorial and registered. Independent of output config-
uration, the two flip-flops are always usable, and always
have at least four product term inputs.
Product terms are available providing asynchronous
resets, flip-flop clocks, and output enables. One reset and
one clock term are provided per flip-flop, with one enable
term per output. Eight product terms provide local synchro-
nous presets, divided up into banks of four and eight flip-
flops. Register preload and buried register observability
simplify testing. The device has an internal power up clear
function.
Functional Logic Diagram ATV2500H/L
2
ATV2500H/L
ATV2500H/L
Functional Logic Diagram Description
The ATV2500H/L Functional Logic Diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the glo-
bal bus.
The ATV2500H/L is a straightforward and uniform PLD.
The twenty-four macrocells are numbered 0 through 23.
Each macrocell contains 17 AND gates. All AND gates
have 172 inputs. The five lower product terms provide AR1,
CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top
twelve product terms are grouped into three sum terms,
which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pat-
tern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macro-
cells sharing Preset 7.
The fourteen dedicated inputs and their complements use
the numbered positions in the global bus as shown. Each
macrocell provides six inputs to the global bus: (left to right)
flip-flop Q2 true and false, flip-flop Q1 true and false, and
the pin true and false. The positions occupied by these sig-
nals in the global bus are the six numbers in the bus dia-
gram next to each macrocell.
Absolute Maximum Ratings*
Temperature Under Bias ............................... -55°C to + 125°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Integrated UV Erase Dose.............................. 7258 W.sec/cm
2
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V dc, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is Vcc + 0.75V dc, which
may overshoot to 7.0V for pulses of less than 20
ns.
3
Output Logic, Registered
Output Logic, Combinatorial
These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
Terms In
S2
0
0
Note:
S1
0
1
S0
0
0
D1
8
12
D2
4
4
(1)
Output Configuration
Registered (Q1)
Registered (Q1)
S2
1
1
1
Note:
S3
0
1
Output Configuration
Active Low
Active High
S3
0
1
S1
0
0
1
S0
0
1
0
Terms In
D1
4
(1)
4
4
(1)
D2
4
4
4
(1)
Output Configuration
Combinatorial (8 Terms)
Combinatorial (4 Terms)
Combinatorial (12 Terms)
1. These 4 terms are shared with D1.
1. These 4 terms are shared with D1.
Output Configuration
Active Low
Active High
DC and AC Operating
ATV2500H-25
Operating
Temperature
(Case)
VCC Power Supply
Com.
Ind.
Mil.
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V
±
10%
ATV2500H/L-30
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V
±
10%
ATV2500H/L-35
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V
±
10%
4
ATV2500H/L
ATV2500H/L
DC Characteristics
Symbol
I
LI
I
LO
I
CC
Parameter
Input Load Current
Output Leakage
Current
Power Supply
Current
Condition
V
IN
= -0.1V to V
CC
+ 1V
V
OUT
= -0.1V to V
CC
+ 0.1V
V
CC
= MAX,
V
IN
= GND or V
CC
Outputs Open
ATV2500L
Com.
Ind.,Mil.
ATV2500H
Com.
Ind.,Mil.
I
OS(1)
V
IL
V
IH
V
OL
V
OH
Note:
Output Short
Circuit Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
IN
= V
IH
or V
IL,
I
OL
= 8 mA Com,Ind; 6 mA Mil.
I
OH
= -100
µA
I
OH
= -4.0 mA
V
CC
- 0.3
2.4
V
OUT
= 0.5V
-0.6
2.0
0.5
0.5
80
80
Min
Typ
Max
10
10
5
10
160
180
-120
0.8
V
CC
+ 0.75
0.5
Units
µA
µA
mA
mA
mA
mA
mA
V
V
V
V
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. This parame-
ter is only sampled and is not 100% tested. See Absolute Maximum Ratings.
Pin Capacitance (f = MHz, T = 25°C)
(1)
°
Typ
C
IN
C
OUT
Note:
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= OV
V
OUT
= OV
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
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