ATT3042-125H68I datasheet, PDF

Datasheet> All Categories > ATT3042-125H68I

Preview

ATT3042-125H68I: DescriptionField-Programmable Gate Arrays; File Size519KB，80 Pages; ManufacturerETC

Download Datasheet View All

ATT3042-125H68I Overview

Field-Programmable Gate Arrays

Preview

Download Datasheet

View All

Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Features

Description

The CMOS ATT3000 Series Field-Programmable

Gate Array (FPGA) family provides a group of high-

density, digital integrated circuits. Their regular,

extendable, ﬂexible, user-programmable array

architecture is composed of a conﬁguration program

store plus three types of conﬁgurable elements: a

perimeter of I/O blocks, a core array of logic blocks,

and resources for interconnection. The general struc-

ture of an FPGA is shown in Figure 1.

The

ORCA

Foundry for ATT3000 Development Sys-

tem provides automatic place and route of netlists.

Logic and timing simulation are available as design

veriﬁcation alternatives. The design editor is used for

interactive design optimization and to compile the

data pattern that represents the conﬁguration pro-

gram.

The FPGA’s user-logic functions and interconnec-

tions are determined by the conﬁguration program

data stored in internal static memory cells. The pro-

gram can be loaded in any of several modes to

accommodate various system requirements. The

program data resides externally in an EEPROM,

EPROM, or ROM on the application circuit board, or

on a ﬂoppy disk or hard disk. On-chip initialization

logic provides for optional automatic loading of pro-

gram data at powerup. A serial conﬁguration PROM

can provide a very simple serial conﬁguration pro-

gram storage.

Xilinx, XC3000,

and

XC3100

are registered trademarks of

Xilinx, Inc.

High performance:

— Up to 270 MHz toggle rates

— 4-input LUT delays <2.7 ns

User-programmable gate arrays

— Unlimited reprogrammability

— Easy design iteration through in-system

logic changes

Flexible array architecture:

— Compatible arrays ranging from 1500 to

6000 gate logic complexity

— Extensive register, combinatorial, and I/O

capabilities

— Low-skew clock nets

— High fan-out signal distribution

— Internal 3-state bus capabilities

— TTL or CMOS input thresholds

— On-chip oscillator ampliﬁer

Standard product availability:

— Low-power 0.55 µm CMOS, static memory

technology

— Pin-for-pin compatible with

Xilinx* XC3000*

and

XC3100*

families

— Cost-effective for volume production

— 100% factory pretested

— Selectable conﬁguration modes

ORCA™

Foundry for ATT3000 Development

System support

All FPGAs processed on a QML-certiﬁed line

Extensive packaging options

Table 1. ATT3000 Series FPGAs

FPGA

ATT3020

ATT3030

ATT3042

ATT3064

ATT3090

Max

Logic

Gates

1,500

2,000

3,000

4,500

6,000

Typical Gate

Range

1,000—1,500

1,500—2,000

2,000—3,000

3,500—4,500

5,000—6,000

Conﬁgurable

Logic

Blocks

100

144

224

320

Array

8x8

10 x 10

12 x 12

16 x 14

20 x 16

User I/Os

Max

120

144

Flip-

Flops

256

360

480

688

928

Horizontal

Long Lines

Conﬁguration

Data Bits

14,779

22,176

30,784

46,064

64,160

Recommended Resources

Adaptive adjustable voltage stabilized power supply circuit

RC circuit diagram for detecting phase sequence reversal

Automatic digital meter inverter power supply circuit diagram

Sound excitation switch circuit

200MHz common source and common gate amplifier circuit

Electronic clock improved circuit diagram

How is medical device design continuing to advance the transition from hospital-based healthcare to home healthcare?: [i=s]This post was last edited by dontium on 2015-1-23 13:17[/i]By Steven A Dean , Director of Medical Product Marketing, Texas InstrumentsIn 2009 , we expect the scattered pieces of this ecosystem pu...; 德州仪器 Analogue and Mixed Signal

Help: cc2430 driver ds18b20 problem: Has anyone done a wireless temperature measurement project based on Zigbee wireless network technology using the cc2430 development board and ds18b20 temperature sensor? I am working on it, but I have...; wwh19910609 RF/Wirelessly

I didn’t receive the launchPad, but I received a FRAM development board.: I don’t know what’s going on?...; campo Microcontroller MCU

GPS Positioning System: I want to use 430 to make a receiver for GPS positioning system, and I'm looking for some advice from seniors who have experience in this field. . ....; lindandaixu NXP MCU

Timer/Counter Mode Control Word: From the previous section, we have learned that the timer/counter in the microcontroller can have multiple uses, so how can I make them work for the purpose I need? This requires setting the timer/cou...; rain MCU

Discussion on the processing method of negative numbers in FPGA: FPGA programming generally involves timing design and other logic circuits, but if FPGA is used for data processing operations, it may involve the processing of negative numbers. For example, if an AD...; eeleader FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components