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ATMEGA168-20MU

Description
8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, QCC32
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size3MB,374 Pages
ManufacturerAtmel (Microchip)
Environmental Compliance
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ATMEGA168-20MU Overview

8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, QCC32

ATMEGA168-20MU Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAtmel (Microchip)
Parts packaging codeQFN
package instructionHVQCCN, LCC32,.2SQ,20
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
Factory Lead Time1 week
core architectureAVR
Device coreAVR
clock speed20
Memory1
flash memory16
were able0
Adc channel8
ADC resolution10
Has ADCYES
Other featuresOPERATES AT 2.7 V MINIMUM SUPPLY AT 10 MHZ
Address bus width
bit size8
CPU seriesAVR RISC
maximum clock frequency20 MHz
DAC channelNO
DMA channelNO
External data bus width
JESD-30 codeS-XQCC-N32
JESD-609 codee3
length5 mm
Humidity sensitivity level1
Number of I/O lines23
Number of terminals32
On-chip program ROM width16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC32,.2SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3/5 V
Certification statusNot Qualified
RAM (bytes)1024
rom(word)8192
ROM programmabilityFLASH
Maximum seat height1 mm
speed20 MHz
Maximum slew rate12 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width5 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
Base Number Matches1
Features
High Performance, Low Power AVR
®
8-Bit Microcontroller
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– 4/8/16K Bytes of In-System Self-Programmable Flash (ATmega48/88/168)
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 256/512/512 Bytes EEPROM (ATmega48/88/168)
Endurance: 100,000 Write/Erase Cycles
– 512/1K/1K Byte Internal SRAM (ATmega48/88/168)
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
– 6-channel 10-bit ADC in PDIP Package
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
2
C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V for ATmega48V/88V/168V
– 2.7 - 5.5V for ATmega48/88/168
Temperature Range:
– -40
°
C to 85
°
C
Speed Grade:
– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Low Power Consumption
– Active Mode:
250 µA at 1 MHz, 1.8V
15 µA at 32 kHz, 1.8V (including Oscillator)
– Power-down Mode:
0.1µA at 1.8V
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega48/V
ATmega88/V *
ATmega168/V *
* Preliminary
Rev. 2545J–AVR–12/06

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