MK32VT832-10YC 98.07.21
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Semiconductor
MK32VT832-10YC
8,388,608 Word x 32 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
DESCRIPTION
The Oki MK32VT832-10YC is a fully decoded, 8,388,608 x 32bit synchronous dynamic
random access memory composed of four 64Mb DRAMs (4Mx16) in TSOP packages
mounted with decoupling capacitors on a 100-pin glass epoxy Dual-in-Line Package
supports any application where high density and large capacity of storage memory are
required, like for example PCs or servers.
FEATURES
•
•
•
•
•
•
•
•
8-Meg Word x 32-Bit (2Bank 4 Byte) organization
100-pin Dual Inline Memory Module
10Ω Damping Resister for DQ and CLK Pins
Single 3.3V power supply, ±0.3V tolerance
Input
:LVTTL compatible
Output :LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
•
/CAS latency (2, 3)
•
Burst length (2, 4, 8)
•
Data scramble(sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
•
•
PRODUCT ORGANIZATION
Product Name
Operation
Frequency (Max.)
100 MHz
Access Time (Max.)
t
AC2
13.0ns
t
AC3
9.0ns
MK32VT832 - 10YC
Note. Specification are subject to change without notice.
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MK32VT832-10YC 98.07.21
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BLOCK DIAGRAM
CKE0
/CS0
DQMB0
DQ0
DQ7
DQMB1
DQ8
DQ15
/CS2
DQMB2
DQ24
DQ31
DQMB3
DQ16
DQ23
UDQM /CS
DQ8
DQ15
LDQM
DQ0
DQ7
CKE
LDQM /CS
DQ0
DQ7
UDQM
DQ8
DQ15
/CS3
LDQM /CS
DQ0
DQ7
UDQM
DQ8
DQ15
Serial PD
SCL
CKE
CKE
CKE1
/CS1
UDQM /CS CKE
DQ8
DQ15
LDQM
DQ0
DQ7
1
3
2
4
5
A0 A1 A2
SDA
1
CLK0
CLK1
3
4
10pF
2
10pF
SA0 SA1 SA2
/RAS,/CAS,/WE
A0-A11,BA0,BA1
1
á
Vcc
4
SDRAMs
Vss
0.22µF x2
Note. The Value of all resistors is 10Ω .
MODULE OUTLINE
(Front)
(Back)
1
51
6
7
56 57
22 23
72 73
50
100
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MK32VT832-10YC 98.07.21
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PIN CONFIGURATION
Front side
Pin No. Pin name
1
VSS
2
DQ0
3
DQ1
4
DQ2
5
DQ3
6
VCC
7
DQ4
8
DQ5
9
DQ6
10
DQ7
11
DQMB0
12
VSS
13
A0
14
A2
15
A4
16
A6
17
A8
18
A10
19
BA1
20
NC
21
VCC
22
NC
23
NC
24
NC
25
CLK0
Back side
Pin No. Pin name
51
VSS
52
DQ8
53
DQ9
54
DQ10
55
DQ11
56
VCC
57
DQ12
58
DQ13
59
DQ14
60
DQ15
61
DQMB1
62
VSS
63
A1
64
A3
65
A5
66
A7
67
A9
68
BA0
69
A11
70
NC
71
VCC
72
/RAS
73
/CAS
74
NC
75
CLK1
Front side
Pin No. Pin name
26
VSS
27
CKE0
28
/WE
29
/CS0
30
/CS2
31
VCC
32
NC
33
NC
34
NC
35
NC
36
VSS
37
DQMB2
38
DQ16
39
DQ17
40
DQ18
41
DQ19
42
VCC
43
DQ20
44
DQ21
45
DQ22
46
DQ23
47
VSS
48
SDA
49
SCL
50
VCC
Back side
Pin No. Pin name
76
VSS
77
CKE1
78
NC
79
/CS1
80
/CS3
81
VCC
82
NC
83
NC
84
NC
85
NC
86
VSS
87
DQMB3
88
DQ24
89
DQ25
90
DQ26
91
DQ27
92
VCC
93
DQ28
94
DQ29
95
DQ30
96
DQ31
97
VSS
98
SA0
99
SA1
100
SA2
Pin Name
VCC
VSS
CLK#
/CS#
CKE#
A0-A11
BA0, BA1
/RAS
/CAS
Function
Power Supply (3.3V)
Ground (0V)
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Pin Name
/WE
DQMB#
DQ#
SDA
SCL
SA#
NC
Function
Write Enable
Data Input / Output Mask
Data Input / Output
Data I/O for SPD
CLK input for SPD
Socket Position Address for SPD
No Connection
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MK32VT832-10YC 98.07.21
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SERIAL PRESENCE DETECT
Byte
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
SPD
Hex Value
80
08
04
0C
08
02
20
00
01
A0
90
00
80
10
00
01
0E
04
06
01
01
00
06
F0
90
00
00
1E
14
1E
3C
08
30
10
30
10
00-00
02
3A
41,45,20,20,20,20,20,20
01 / 06
Remark
Defines the number of bytes written into
SPD memory
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
Number of columns
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
Cycle time (CL=3)
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
128 byte
Notes
256 byte
SDRAM
12 rows
8 columns
2 bank
32 bits
0
LVTTL
CL=3 t
CC
=10ns
CL=3 t
AC3
=9ns
None Parity
Normal / Self
x16
t
CCD
: 1 CLK
2, 4, 8
4 banks
2, 3
0
0
CL=2 t
CC2
=15ns
CL=2 t
AC2
=9ns
Not support
Not support
t
RP
=30ns
t
RRD
=20ns
t
RCD
=30ns
t
RAS
=60ns
32MB
Command and address signal input setup time
3ns
Command and address signal input hold time
1ns
Data signal input setup time
3ns
Data signal input hold time
1ns
Superset Information
R.F.U
SPD data revision code
02
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
MK32VT832-10YC
4D,4B,33,32,56,54,38,33,32,
2D,31,30,59,43,20,20,20,20
20, 20
91, 92
00-00
93-125
66
126
06
127
FF-FF
128-255
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
66MHz
CL=2,3
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MK32VT832-10YC 98.07.21
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Voltage on any pin relative to Vss
Vcc supply voltage
Storage temperature
Power dissipation
Short circuit current
Operating temperature
Symbol
V
IN
, V
OUT
Vcc, VccQ
Tstg
P
D
*
I
OS
Topr
Value
-0.5 to Vcc+0.5
-0.5 to 4.6
- 55 to 150
4
50
0 to 70
Unit
V
V
°C
W
mA
°C
*: Ta=25
°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Power supply voltage
Input high voltage
Input low voltage
Symbol
Vcc, VccQ
V
IH
V
IL
Min.
3.0
2.0
-0.3
Typ.
3.3
-
-
Max.
3.6
Vcc+0.3
0.8
Unit
V
V
V
Capacitance
(Vcc=3.3V
±
0.3V, Ta=25 °C f=1MHz)
Parameter
Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE)
Input capacitance (/CS0-/CS3)
Input capacitance (DQMB0-DQMB3)
Input capacitance (CKE0,CKE1)
I/O capacitance (DQ0-DQ32)
Input capacitance (CLK0, CLK1)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
I/O
C
CLK
Max.
27
16
16
16
20
25
Unit
pF
pF
pF
pF
pF
pF
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