Features
•
High-performance, Low-power AVR
®
8-bit Microcontroller
•
Advanced RISC Architecture
– 130 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz
– On-chip 2-cycle Multiplier
Program and Data Memories
– 16K Bytes of Nonvolatile In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– Optional Boot Code Memory with Independent Lock Bits
Self-programming of Program and Data Memories
– 512 Bytes Nonvolatile In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K Bytes Internal SRAM
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9- or 10-bit PWM
– Dual Programmable Serial UARTs
– Master/Slave SPI Serial Interface
– Real Time Counter with Separate Oscillator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power Save and Power-down
I/O and Packages
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-pin PLCC and TQFP
Operating Voltages
– 2.7V - 5.5V (ATmega161L), 4.0V - 5.5V (ATmega161)
Speed Grades
– 0 - 4 MHz (ATmega161L), 0 - 8 MHz (ATmega161)
Commercial and Industrial Temperature Ranges
•
•
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega161
ATmega161L
Advance
Information
•
•
•
•
•
Rev. 1228A–08/99
1
Pin Configurations
(OC0/T0) PB0
(OC2/T1) PB1
(RXD1/AIN0) PB2
(TXD1/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
(TXD0) PD1
(INT0) PD2
(INT1) PD3
(TOSC1) PD4
(OC1A/TOSC2) PD5
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
TQFP
PB4 (SS)
PB3 (TXD1/AIN1)
PB2 (RXD1/AIN0)
PB1 (OC2/T1)
PB0 (OC0/T0)
NC*
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PLCC
PB4 (SS)
PB3 (TXD1/AIN1)
PB2 (RXD1/AIN0)
PB1 (OC2/T1)
PB0 (OC0/T0)
NC*
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
NC*
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
* NC = Do not connect
(Can be used in future devices)
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
NC*
(A8) PC0
(A9) PC1
(A10) PC2
(A11) PC3
(A12) PC4
44
43
42
41
40
39
38
37
36
35
34
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
NC*
(TXD0) PD1
(INT0) PD2
(INT1) PD3
(TOSC1) PD4
(OCIA/TOSC2) PD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE0 (ICP/INT2)
NC*
PE1 (ALE)
PE2 (OC1B)
PC7 (A15)
PC6 (A14)
PC5 (A13)
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
(RXD0) PD0
NC*
(TXD0) PD1
(INT0) PD2
(INT1) PD3
(TOSC1) PD4
(OC1A/TOSC2) PD5
Description
The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful
instructions in a single clock cycle, the ATmega161 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.The AVR core combines a rich instruction set with
32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC
microcontrollers.
The ATmega161 provides the following features: 16K bytes of In-System- or Self-programmable Flash, 512 bytes
EEPROM, 1K bytes SRAM, 35 general purpose I/O lines, 32 general purpose working registers, Real Time Counter, three
flexible timer/counters with compare modes, internal and external interrupts, two programmable serial UARTs, programma-
ble Watchdog Timer with internal oscillator, an SPI serial port and three software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The
power-down mode saves the register and SRAM contents but freezes the oscillator, disabling all other chip functions until
the next external interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash program mem-
ory can be reprogrammed using the self-programming capability through the bootblock, using an ISP through the SPI-port,
or by using a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel ATmega161 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega161 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2
ATmega161(L)
(WR) PD6
(RD) PD7
XTAL2
XTAL1
GND
NC*
(A8) PC0
(A9) PC1
(A10) PC2
(A11) PC3
(A12) PC4
* NC = Do not connect
(Can be used in future devices)
ATmega161(L)
Block Diagram
Figure 1.
The ATmega161 Block Diagram
PA0-PA7
PC0-PC7
VCC
PORTA DRIVERS
PORTC DRIVERS
GND
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
XTAL1
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
XTAL2
RESET
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
UARTS
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA DIR
DATA REG.
REG. PORTE
PORTE
+
-
PORTB DRIVERS
PORTD DRIVERS
PORTE DRIVERS
PB0 - PB7
PD0 - PD7
PE0 - PE2
3
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A
output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are
externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
Port A serves as Multiplexed Address/Data port when using external memory interface.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega161 as listed on page 80.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port C also serves as Address high output when using external memory interface.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega161 as listed on page 87.
Port E (PE2..PE0)
Port E is a 3-bit bidirectional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega161 as listed on page 93.
RESET
Reset input. A low level on this pin for more than 500 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
4
ATmega161(L)
ATmega161(L)
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2.
Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
XTAL2
XTAL1
GND
Note:
When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
Figure 3.
External Clock Drive Configuration
5
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