ATMEGA128-8AC datasheet, PDF - EEWORLD Datasheet

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ATMEGA128-8AC: Description8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size132KB，16 Pages; ManufacturerAtmel (Microchip)

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ATMEGA128-8AC Overview

8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64

ATMEGA128-8AC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	TQFP, TQFP64,.63SQ,32
Contacts	64
Reach Compliance Code	compli
core architecture	AVR
Device core	AVR
clock speed	16
Memory	4
flash memory	128
were able	0
Adc channel	8
ADC resolution	10
Has ADC	YES
Address bus width	16
bit size	8
CPU series	AVR RISC
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of I/O lines	53
Number of terminals	64
On-chip program ROM width	16
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Encapsulate equivalent code	TQFP64,.63SQ,32
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	4096
rom(word)	65536
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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Features

•

High-performance, Low-power AVR

8-bit Microcontroller

•

Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

– 128K Bytes of In-System Reprogrammable Flash

Endurance: 1,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 4K Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 4K Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

– SPI Interface for In-System Programming

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and

Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain (1x, 10x, 200x)

– Byte-oriented 2-wire Serial Interface

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

– Software Selectable Clock Frequency

– ATmega103 Compatibility Mode Selected by a Fuse

– Global Pull-up Disable

I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP

Operating Voltages

– 2.7 - 5.5V (ATmega128L)

– 4.5 - 5.5V (ATmega128)

Speed Grades

– 0 - 8 MHz (ATmega128L)

– 0 - 16 MHz (ATmega128)

•

8-bit

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

ATmega128

ATmega128L

Preliminary

Summary

•

Rev. 2467AS-08/01

Note: This is a summary document. A complete document is

available on our web site at

www.atmel.com.

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega128 provides the following features: 128K bytes of In-System Programma-

ble Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53

general-purpose I/O lines, 32 general purpose working registers, Real Time Counter

(RTC), four flexible timer/counters with compare modes and PWM, 2 USARTs, a byte

oriented 2-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input

stage with programmable gain, programmable Watchdog Timer with internal oscillator,

an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for

accessing the On-chip Debug system and programming and six software selectable

power saving modes. The Idle mode stops the CPU while allowing the SRAM,

timer/counters, SPI port, and interrupt system to continue functioning. The Power-down

mode saves the register contents but freezes the oscillator, disabling all other chip func-

tions until the next interrupt or hardware reset. In Power-save mode, the asynchronous

timer continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping. The ADC Noise Reduction Mode stops the CPU and all I/O modules

except asynchronous timer and ADC, to minimize switching noise during ADC conver-

sions. In Standby mode, the crystal/resonator oscillator is running while the rest of the

device is sleeping. This allows very fast start-up combined with low power consumption.

In Extended Standby mode, both the main oscillator and the asynchronous timer con-

tinue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The on-chip ISP Flash allows the program memory to be reprogrammed in-system

through an SPI serial interface, by a conventional nonvolatile memory programmer, or

by an on-chip Boot program running on the AVR core. The boot program can use any

interface to download the application program in the application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is

a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega128 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators, and evaluation kits.

ATmega103 and

ATmega128

Compatibility

The ATmega128 is a highly complex microcontroller where the number of I/O locations

supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward

compatibility with the ATmega103, all I/O locations present in ATmega103 have the

same location in ATmega128. Most additional I/O locations are added in an Extended

I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These

location can be reached by using LD/LDS/LDD and ST/STS/STD instruction only, not by

using IN and OUT instruction. The relocation of the internal RAM space may still be a

problem for ATmega103 users. Also, the increased number of interrupt vectors might be

a problem if the code uses absolute addresses. To solve these problems, an

ATmega103 compatibility mode can be selected by programming the fuse M103C. In

this mode, none of the functions in the Extended I/O space are in use, so the internal

RAM is located as in ATmega103. Also, the extended interrupt vectors are removed.

ATmega128(L)

2467AS–08/01

ATmega128(L)

The ATmega128 is 100% pin compatible with ATmega103, and can replace the

ATmega103 on current Printed Circuit Boards. The application note “Replacing

ATmega103 by ATmega128” describes what the user should be aware of replacing the

ATmega103 by an ATmega128.

ATmega103 Compatibility

Mode

By programming the M103C fuse, the ATmega128 will be compatible with the

ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. How-

ever, some new features in ATmega128 are not available in this compatibility mode,

these features are listed below:

•

One USART instead of two, asynchronous mode only. Only the 8 least significant

bits of the Baud Rate Register is available.

One 16 bits Timer/Counter with 2 compare registers instead of two 16-bit

Timer/Counters with 3 compare registers.

2-wire serial interface is not supported.

Port G serves alternate functions only (not a general I/O port).

Port F serves as digital input only in addition to analog input to the ADC.

Boot Loader capabilities is not supported.

It is not possible to adjust the frequency of the internal calibrated RC oscillator.

The External Memory Interface can not release any Address pins for general I/O,

neither configure different wait-states to different External Memory Address

sections.

Pin Descriptions

VCC

GND

Port A (PA7..PA0)

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega128 as listed

page 68.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega128 as listed

page 69.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

2467AS–08/01

ATMEGA128-8AC Related Products

	ATMEGA128-8AC	ATMEGA12816A	ATM128	ATMEGA128-8AI
Description	8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64	8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64	8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64	8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
Address bus width	16	16	16	16
External data bus width	8	8	8	8
Number of terminals	64	64	64	64
Maximum operating temperature	70 °C	85 Cel	85 Cel	85 °C
Minimum operating temperature	-	-40 Cel	-40 Cel	-40 °C
PWM channel	YES	Yes	Yes	YES
surface mount	YES	Yes	Yes	YES
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal location	QUAD	Four	Four	QUAD

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