AT91CAPS9500A-CJ datasheet, PDF

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AT91CAPS9500A-CJ: DescriptionCustomizable Microcontroller Processor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size487KB，52 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT91CAPS9500A-CJ Overview

Customizable Microcontroller Processor

AT91CAPS9500A-CJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	225
Reach Compliance Code	compli
Has ADC	YES
Other features	ALSO REQUIRES 3.3V SUPPLY
Address bus width	26
bit size	16
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	YES
External data bus width	32
JESD-30 code	S-PBGA-B225
length	13 mm
Number of I/O lines	90
Number of terminals	225
On-chip program ROM width	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
RAM (bytes)	163840
rom(word)	65536
ROM programmability	FASTROM
Maximum seat height	1.7 mm
speed	240 MHz
Maximum supply voltage	1.32 V
Minimum supply voltage	1.08 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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Features

•

Incorporates the ARM926EJ-S

™

ARM

Thumb

Processor

– DSP Instruction Extensions, ARM Jazelle

Technology for Java

Acceleration

– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer

– 220 MIPS at 200 MHz

– Memory Management Unit

– EmbeddedICE

™

In-circuit Emulation, Debug Communication Channel Support

Additional Embedded Memories

– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed

– One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed

External Bus Interface (EBI)

– EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory,

Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash

™

Metal Programmable (MP) Block

– 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers)

for AT91CAP9S500A/AT91CAP9S250A Respectively

– Ten 512 x 36-bit Dual Port RAMs

– Eight 512 x 72-bit Single Port RAMs

– High Connectivity for Up to Three AHB Masters and Four AHB Slaves

– Up to Seven AIC Interrupt Inputs

– Up to Four DMA Hardware Handshake Interfaces

– Delay Lines for Double Data Rate Interface

– UTMI+ Full Connection

– Up to 77 Dedicated I/Os

LCD Controller

– Supports Passive or Active Displays

– Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode

– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider

Screen Buffers

Image Sensor Interface

– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate

– 12-bit Data Interface for Support of High Sensibility Sensors

– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format

USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port

– Dual On-chip Transceivers

– Integrated FIFOs and Dedicated DMA Channels

USB 2.0 High Speed (480 Mbits per second) Device Port

– On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM

– Integrated FIFOs and Dedicated DMA Channels

– Integrated UTMI+ Physical Interface

Ethernet MAC 10/100 Base T

– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)

– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit

Multi-Layer Bus Matrix

– Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus

Bandwidth at Maximum 100 MHz System Clock Speed

– Boot Mode Select Option, Remap Command

Fully-featured System Controller, Including

– Reset Controller, Shutdown Controller

•

Customizable

Microcontroller

Processor

AT91CAP9S500A

AT91CAP9S250A

Summary

Preliminary

•

6264AS–CAP–21-May-07

AT91CAPS9500A-CJ Related Products

	AT91CAPS9500A-CJ	AT91CAPS250A-CJ
Description	Customizable Microcontroller Processor	Customizable Microcontroller Processor
Is it Rohs certified?	conform to	conform to
Maker	Atmel (Microchip)	Atmel (Microchip)
Parts packaging code	BGA	BGA
package instruction	LFBGA,	LFBGA,
Contacts	225	225
Reach Compliance Code	compli	compli
Has ADC	YES	YES
Other features	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY
Address bus width	26	26
bit size	16	16
maximum clock frequency	16 MHz	16 MHz
DAC channel	NO	NO
DMA channel	YES	YES
External data bus width	32	32
JESD-30 code	S-PBGA-B225	S-PBGA-B225
length	13 mm	13 mm
Number of I/O lines	90	90
Number of terminals	225	225
On-chip program ROM width	32	32
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
PWM channel	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
RAM (bytes)	163840	163840
rom(word)	65536	65536
ROM programmability	FASTROM	FASTROM
Maximum seat height	1.7 mm	1.7 mm
speed	240 MHz	240 MHz
Maximum supply voltage	1.32 V	1.32 V
Minimum supply voltage	1.08 V	1.08 V
Nominal supply voltage	1.2 V	1.2 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	13 mm	13 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC
Base Number Matches	1	1

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