Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100% Compatible to AT45D021
Single 2.7V - 3.6V Supply
Serial Interface Architecture
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Pages (264 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
Internal Program and Control Timer
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
13 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
2-megabit
2.7-volt Only
Serial
DataFlash
®
AT45DB021A
Recommend using
AT45DB021B for new
designs.
Description
The AT45DB021A is a 2.7-volt only, serial interface Flash memory suitable for
in-system reprogramming. Its 2,162,688 bits of memory are organized as 1024 pages
of 264 bytes each. In addition to the main memory, the AT45DB021A also contains
two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash
(continued)
Pin Configurations
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
PLCC
CS
NC
NC
GND
VCC
NC
NC
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TSOP Top View
Type 1
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DC
DC
NC
NC
NC
14
15
16
17
18
19
20
SCK
SI
SO
NC
NC
NC
NC
NC
NC
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
Rev. 1642C–01/01
Note: PLCC package pins 16
and 17 are DON’T CONNECT.
1
memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses a
serial interface to sequentially access its data. The simple
serial interface facilitates hardware layout, increases sys-
tem reliability, minimizes switching noise, and reduces
package size and active pin count. The device is optimized
for use in many commercial and industrial applications
where high density, low pin count, low voltage, and low
power are essential. Typical applications for the DataFlash
are digital voice storage, image storage, and data storage.
The device operates at clock frequencies up to 13 MHz
with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB021A does not require high input voltages for pro-
gramming. The device operates from a single power
supply, 2.7V to 3.6V, for both the program and read opera-
tions. The AT45DB021A is enabled through the chip select
pin (CS) and accessed via a three-wire interface consisting
of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the
AT45DB021A is divided into three levels of granularity
comprised of sectors, blocks and pages. The Memory
Architecture Diagram illustrates the breakdown of each
level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page-
by-page basis; however, the optional erase operations can
be performed at the block or page level.
2
AT45DB021A
AT45DB021A
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
PAGE ARCHITECTURE
8 Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR 1
BLOCK 2
SECTOR 1 = 248 Pages
65,472 bytes (62K + 1984)
PAGE 6
PAGE 7
PAGE 8
BLOCK 30
BLOCK 31
SECTOR 2 = 256 Pages
67,584 bytes (64K + 2K)
SECTOR 2
BLOCK 33
BLOCK 1
BLOCK 32
PAGE 9
PAGE 14
PAGE 15
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 3 = 512 Pages
135,168 bytes (128K + 4K)
PAGE 16
PAGE 17
PAGE 18
PAGE 1021
BLOCK 126
BLOCK 127
PAGE 1022
PAGE 1023
Block = 2112 bytes
(2K + 64)
Page = 264 bytes
(256 + 8)
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Tables 1 through 4 (pages 8 and
9). A valid instruction starts with the falling edge of CS fol-
lowed by the appropriate 8-bit opcode and the desired
buffer or main memory address location. While the CS pin
is low, toggling the SCK pin controls the loading of the
opcode and the desired buffer or main memory address
location through the SI (serial input) pin. All instructions,
addresses, and data are transferred with the most signifi-
cant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the
terminology BFA8 - BFA0 to denote the nine address bits
required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology
PA9 - PA0 and BA8 - BA0 where PA9 - PA0 denotes the
10 address bits required to designate a page address and
BA8-BA0 denotes the nine address bits required to desig-
nate a byte address within the page.
or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 8 for
a complete list) is used to select which category will be
used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the
clock cycle sequences for each mode.
CONTINUOUS ARRAY READ:
By supplying an initial
starting address for the main memory array, the Continu-
ous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply
providing a clock signal; no additional addressing informa-
tion or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automati-
cally increment on every clock cycle, allowing one
continuous read operation without the need of additional
address sequences. To perform a continuous read, an
opcode of 68H or E8H must be clocked into the device fol-
lowed by 24 address bits and 32 don’t care bits. The first
five bits of the 24-bit address sequence are reserved for
upward and downward compatibility to larger and smaller
density devices (see Notes under “Command Sequence for
Read/Write Operations” diagram). The next 10 address bits
(PA9 -PA0) specify which page of the main memory array
to read, and the last nine bits (BA8 - BA0) of the 24-bit
address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address
bits are needed to initialize the read operation. Following
the 32 don’t care bits, additional clock pulses on the SCK
pin will result in serial data being output on the SO (serial
output) pin.
3
Read Commands
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences
between the modes are in respect to the inactive state of
the SCK signal as well as which clock cycle data will begin
to be output. The two categories, which are comprised of
four modes total, are defined as Inactive Clock Polarity Low
The CS pin must remain low during the loading of the
opcode, the address bits, the don’t care bits, and the read-
ing of data. When the end of a page in main memory is
reached during a Continuous Array Read, the device will
continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the
crossover from the end of one page to the beginning of the
next page). When the last bit in the main memory array has
been read, the device will continue reading back at the
beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when
wrapping around from the end of the array to the beginning
of the array.
A low-to-high transition on the CS pin will terminate the
read operation and tri-state the SO pin. The maximum SCK
frequency allowable for the Continuous Array Read is
defined by the f
CAR
specification. The Continuous Array
Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
BURST ARRAY READ:
The Burst Array Read operation
functions almost identically to the Continuous Array Read
operation but allows much higher read throughputs by uti-
lizing faster clock frequencies. The Burst Array Read
command allows the device to burst an entire page of data
out at the maximum SCK frequency defined by the f
BAR
parameter. Differences between the Burst Array Read and
Continuous Array Read operations are limited to timing
only. The opcodes utilized and the opcode and addressing
sequence for the Burst Array Read are identical to the Con-
tinuous Array Read. The opcode of 68H or E8H must be
clocked into the device followed by the 24 address bits and
32 don’t care bits. Following the 32 don’t care bits, addi-
tional clock pulses on the SCK pin will result in serial data
being output on the SO (serial output) pin.
As with the Continuous Array Read, the CS pin must
remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. During a
Burst Array Read, when the end of a page in main memory
is reached (the last bit of the page has been clocked out),
the system must delay the next SCK pulse by a minimum
time of t
BRBD
. This delay is necessary to allow the device
enough time to cross over the burst read boundary, which
is defined as the end of one page in memory to the begin-
ning of the next page. When the last bit in the main memory
array has been read, the device will continue reading back
at the beginning of the first page of memory. The transition
from the last bit of the array back to the beginning of the
array is also considered a burst read boundary. Therefore,
the system must delay the SCK pulse that will be used to
read the first bit of the memory array by a minimum time of
t
BRBD
.
A low-to-high transition on the CS pin will terminate the
read operation and tri-state the SO pin. The maximum SCK
frequency allowable for the Burst Array Read is defined by
4
the f
BAR
specification. The Burst Array Read bypasses both
data buffers and leaves the contents of the buffers
unchanged.
MAIN MEMORY PAGE READ:
A Main Memory Page Read
allows the user to read data directly from any one of the
1024 pages in the main memory, bypassing both of the
data buffers and leaving the contents of the buffers
unchanged. To start a page read, an opcode of 52H or D2H
must be clocked into the device followed by 24 address bits
and 32 don’t care bits. The first five bits of the 24-bit
address sequence are reserved bits, the next 10 address
bits (PA9 - PA0) specify the page address, and the next
nine address bits (BA8 - BA0) specify the starting byte
address within the page. The 32 don’t care bits which fol-
low the 24 address bits are sent to initialize the read
operation. Following the 32 don’t care bits, additional
pulses on SCK result in serial data being output on the SO
(serial output) pin. The CS pin must remain low during the
loading of the opcode, the address bits, the don’t care bits
and the reading of data. When the end of a page in main
memory is reached during a Main Memory Page Read, the
device will continue reading at the beginning of the same
page. A low-to-high transition on the CS pin will terminate
the read operation and tri-state the SO pin.
BUFFER READ:
Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H or D4H is used to read data
from buffer 1, and an opcode of 56H or D6H is used to read
data from buffer 2. To perform a Buffer Read, the eight bits
of the opcode must be followed by 15 don’t care bits, nine
address bits, and eight don’t care bits. Since the buffer size
is 264-bytes, nine address bits (BFA8-BFA0) are required
to specify the first byte of data to be read from the buffer.
The CS pin must remain low during the loading of the
opcode, the address bits, the don’t care bits and the read-
ing of data. When the end of a buffer is reached, the device
will continue reading back at the beginning of the buffer. A
low-to-high transition on the CS pin will terminate the read
operation and tri-state the SO pin.
STATUS REGISTER READ:
The status register can be
used to determine the device’s ready/busy status, the
result of a Main Memory Page to Buffer Compare opera-
tion, or the device density. To read the status register, an
opcode of 57H or D7H must be loaded into the device.
After the last bit of the opcode is shifted in, the eight bits of
the status register, starting with the MSB (bit 7), will be
shifted out on the SO pin during the next eight clock cycles.
The five most-significant bits of the status register will con-
tain device information, while the remaining three least-
significant bits are reserved for future use and will have
undefined values. After bit 0 of the status register has been
shifted out, the sequence will repeat itself (as long as CS
remains low and SCK is being toggled) starting again with
bit 7. The data in the status register is constantly updated,
so each repeating sequence will output new data.
AT45DB021A
AT45DB021A
Status Register Format
Bit 7
RDY/BUSY
Bit 6
COMP
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
X
Bit 1
X
Bit 0
X
Ready/Busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations that can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-in Erase,
Buffer to Main Memory Page Program without Built-in
Erase, Page Erase, Block Erase, Main Memory Page Pro-
gram, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer
Compare operation is indicated using bit 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device density is indicated using bits 5, 4, and 3 of the
status register. For the AT45DB021A, the three bits are 0,
1, and 0. The decimal value of these three binary bits does
not equate to the device density; the three bits represent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
part will first erase the selected page in main memory to all
1s and then program the data stored in the buffer into the
specified page in the main memory. Both the erase and the
programming of the page are internally self-timed and
should take place in a maximum time of t
EP
. During this
time, the status register will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE:
A previously erased page within
main memory can be programmed with the contents of
either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode (88H for buffer 1 or 89H for buffer 2) must be fol-
lowed by the five reserved bits, 10 address bits (PA9-PA0)
that specify the page in the main memory to be written, and
nine additional don’t care bits. When a low-to-high transi-
tion occurs on the CS pin, the part will program the data
stored in the buffer into the specified page in the main
memory. It is necessary that the page in main memory that
is being programmed has been previously erased. The pro-
gramming of the page is internally self-timed and should
take place in a maximum time of t
P
. During this time, the
status register will indicate that the part is busy.
PAGE ERASE:
The optional Page Erase command can be
used to individually erase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later
time. To perform a Page Erase, an opcode of 81H must be
loaded into the device, followed by five reserved bits,
10 address bits (PA9- PA0), and nine don’t care bits. The
nine address bits are used to specify which page of the
memory array is to be erased. When a low-to-high transi-
tion occurs on the CS pin, the part will erase the selected
page to 1s. The erase operation is internally self-timed and
should take place in a maximum time of t
PE
. During this
time, the status register will indicate that the part is busy.
BLOCK ERASE:
A block of eight pages can be erased at
one time allowing the Buffer to Main Memory Page Pro-
gram without Built-in Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by five
reserved bits, seven address bits (PA9-PA3), and 12 don’t
care bits. The seven address bits are used to specify which
block of eight pages is to be erased. When a low-to-high
transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is
internally self-timed and should take place in a maximum
time of t
BE
. During this time, the status register will indicate
that the part is busy.
Program and Erase Commands
BUFFER WRITE:
Data can be shifted in from the SI pin
into either buffer 1 or buffer 2. To load data into either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
must be followed by 15 don't care bits and nine address
bits (BFA8- BFA0). The nine address bits specify the first
byte in the buffer to be written. The data is entered follow-
ing the address bits. If the end of the data buffer is reached,
the device will wrap around back to the beginning of the
buffer. Data will continue to be loaded into the buffer until a
low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE:
Data written into either buffer 1 or buffer
2 can be programmed into the main memory. To start the
operation, an 8-bit opcode (83H for buffer 1 or 86H for
buffer 2) must be followed by the five reserved bits, 10
address bits (PA9 -PA0) that specify the page in the main
memory to be written, and nine additional don’t care bits.
When a low-to-high transition occurs on the CS pin, the
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
