August 2005
rev 0.2
Low Power Mobile VGA EMI Reduction IC
Features
FCC approved method of EMI attenuation
Provides up to 15dB EMI reduction
Generates a low EMI spread spectrum clock
and a non-spread Reference Clock of the input
frequency
Optimized for frequency range from 20MHz to
40MHz
Internal loop filter minimizes external components
and board space
Down Spread Deviation: -1.25%
Low inherent Cycle-to-Cycle jitter
3.3V Operating Voltage
CMOS/TTL compatible inputs and outputs
Low power CMOS design
Supports notebook VGA and other LCD timing
controller applications
Power Down function for mobile application
Products are available for industrial temperature
range.
Available in 8 pin SOIC and TSSOP Packages
ASM3P1819N
The ASM3P1819N reduces electromagnetic interference
(EMI) at the clock source, allowing a system wide EMI
reduction for all the down stream clocks and data
dependent signals. The ASM3P1819N allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass
EMI
regulations.
The ASM3P1819N modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
thereby decreasing the peak amplitude of its harmonics.
This result in significantly lower system EMI compared to
the typical narrow band signal produced by oscillators and
most clock generators.
Lowering EMI by increasing a signal’s bandwidth is called
“spread spectrum clock generation”. The ASM3P1819N
uses the most efficient and optimized modulation profile
approved by the FCC and is implemented by using a
proprietary all digital method
Applications
The ASM3P1819N is targeted towards EMI management
Functional Description
The
ASM3P1819N
is
a
versatile
spread
spectrum
frequency modulator designed specifically for a wide range
of input clock frequencies from 20 to 40MHz. The
ASM3P1819N can generate an EMI reduced clock from
crystal, ceramic resonator, or system clock.
for memory and LVDS interfaces in mobile graphic chipsets
and high-speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
system.
Block Diagram
PD#
VDD
XIN
Crystal
Oscillator
XOUT
Frequency
Divider
Feedback
Divider
Modulation
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
REF
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2005
rev 0.2
Pin Configuration
XIN
VSS
NC
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
ASM3P1819N
ASM3P1819N
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN
VSS
NC
ModOUT
REF
PD#
VDD
XOUT
Type
I
P
-
O
O
I
P
I
Description
Connect to externally generated Clock signal or Crystal.
Ground Connection. Connect to system ground.
No Connect.
Spread spectrum clock output.
Non-modulated Reference clock output of the input frequency.
Power down control pin. Pull LOW to enable Power-Down mode. This pin
has an internal pull-up resistor.
Connect to +3.3V.
Connect to crystal. No connect if externally generated clock signal is used.
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Output Frequency and Modulation Rate
Input Frequency Range
(MHz)
20 to 40
Output Frequency Range
(MHz)
20 to 40
Modulation Rate
Input Frequency / 512
Spread Deviation
(%)
-1.25
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 7
August 2005
rev 0.2
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
ASM3P1819N
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
VDD
t
ON
Z
OUT
Input Low voltage
Input High voltage
Input Low current
Input High current
Parameter
Min
VSS – 0.3
2.0
-
-
-
-
-
2.5
7.1
f
IN - min
-
-
-
-
Typ
-
-
-
-
3
3
-
-
-
4.5
3.3
0.18
50
Max
0.8
VDD + 0.3
-20.0
1.0
-
-
0.4
-
26.9
f
IN - max
-
-
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
X
OUT
Output low current @ 0.4V, VDD = 3.3V
X
OUT
Output high current @ 2.5V, VDD = 3.3V
Output Low voltage VDD = 3.3V, I
OL
= 20mA
Output High voltage VDD = 3.3V, I
OH
= 20mA
Dynamic Supply current
3.3V and 10pF probe loading
Static Supply current
Operating Voltage
Power up time (First locked clock cycle after power up)
Clock Output impedance
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH1
t
HL1
t
JC
t
D
Input Frequency
Output Frequency
Output Rise time
( Measured from 0.8V to 2.0V )
Output Fall time
( Measured from 2.0V to 0.8V )
Jitter (Cycle to Cycle)
Output Duty cycle
Parameter
Min
20
20
-
-
-200
45
Typ
-
-
0.69
0.66
-
50
Max
40
40
-
-
200
55
Unit
MHz
MHz
nS
nS
pS
%
Note:1. t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 7
Embedded System
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