BSS119N
OptiMOS
™
Small-Signal-Transistor
Features
• N-channel
• Enhancement mode
• Logic level (4.5V rated)
• Avalanche rated
• Qualified according to AEC Q101
• 100% lead-free; RoHS compliant; Halogen free
Product Summary
V
DS
R
DS(on),max
V
GS
=10 V
V
GS
=4.5 V
I
D
100
6
10
0.19
A
V
W
PG-SOT23
3
1
2
Type
BSS119N
Package
SOT23
Tape and Reel Information
H6327: 3000 pcs/ reel
Marking
sSH
Halogen free
Packing
Yes
Non dry
Maximum ratings,
at
T
j
=25 °C, unless otherwise specified
Parameter
Continuous drain current
Symbol Conditions
I
D
T
A
=25 °C
T
A
=70 °C
Pulsed drain current
Avalanche energy, single pulse
I
D,pulse
E
AS
T
A
=25 °C
I
D
=0.19 A,
R
GS
=25
W
I
D
=0.19 A,
V
DS
=80 V,
di /dt =200 A/µs,
T
j,max
=150 °C
Value
0.19
0.15
0.77
2.0
mJ
Unit
A
Reverse diode dv /dt
dv /dt
6
kV/µs
Gate source voltage
Power dissipation
1)
Operating and storage temperature
ESD Class
Soldering Temperature
IEC climatic category; DIN IEC 68-1
V
GS
P
tot
T
j
,
T
stg
JESD22-A114 -HBM
T
A
=25 °C
±20
0.5
-55 ... 150
0 (<250V)
260 °C
55/150/56
V
W
°C
Rev 2.1
page 1
2012-05-10
BSS119N
Parameter
Symbol Conditions
min.
Thermal characteristics
Thermal resistance,
junction - ambient
Values
typ.
max.
Unit
R
thJA
minimal footprint
1)
-
-
250
K/W
Electrical characteristics,
at
T
j
=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Drain-source leakage current
V
(BR)DSS
V
GS
=0 V,
I
D
=250 µA
V
GS(th)
I
DSS
V
DS
=Vgs V,
I
D
=13 µA
V
DS
=100 V,
V
GS
=0 V,
T
j
=25 °C
V
DS
=100 V,
V
GS
=0 V,
T
j
=150 °C
Gate-source leakage current
Drain-source on-state resistance
I
GSS
R
DS(on)
V
GS
=20 V,
V
DS
=0 V
V
GS
=4.5 V,
I
D
=0.15 A
V
GS
=10 V,
I
D
=0.19 A
Transconductance
g
fs
|V
DS
|>2|I
D
|R
DS(on)max
,
I
D
=0.15 A
100
1.3
-
-
1.9
-
-
2.3
0.01
mA
V
-
-
-
-
-
-
2915
2406
0.35
5
10
nA
10000 mW
6000
-
S
1)
Performed on 40mm² FR4 PCB. The traces are 1mm wide, 70µm thick and 20mm long; they are present on both
sides of the PCB
Rev 2.1
page 2
2012-05-10
BSS119N
Parameter
Symbol Conditions
min.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Reverse Diode
Diode continous forward current
Diode pulse current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
I
S
I
S,pulse
V
SD
t
rr
Q
rr
V
GS
=0 V,
I
F
=0.19 A,
T
j
=25 °C
V
R
=50 V,
I
F
=0.19 A,
di
F
/dt =100 A/µs
-
T
A
=25 °C
-
-
-
-
-
0.8
12
5
0.77
1.1
-
-
V
ns
nC
-
0.19
A
Q
gs
Q
gd
Q
g
V
plateau
V
DD
=50 V,
I
D
=0.19 A,
V
GS
=0 to 10 V
-
-
-
-
0.05
0.25
0.6
3.2
-
-
-
-
V
nC
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DD
=50 V,
V
GS
=10 V,
I
D
=0.19 A,
R
G
=6
W
V
GS
=0 V,
V
DS
=25 V,
f
=1 MHz
-
-
-
-
-
-
-
15.7
3.4
2.1
2.7
3.3
7.0
18.8
20.9
4.5
3.1
-
-
-
-
ns
pF
Values
typ.
max.
Unit
Rev 2.1
page 3
2012-05-10
BSS119N
1 Power dissipation
P
tot
=f(T
A
)
2 Drain current
I
D
=f(T
A
);
V
GS
≥10 V
0.6
0.2
0.5
0.15
0.4
P
tot
[W]
0.3
I
D
[A]
0
40
80
120
160
0.1
0.2
0.05
0.1
0
0
0
40
80
120
160
T
A
[°C]
T
A
[°C]
3 Safe operating area
I
D
=f(V
DS
);
T
A
=25 °C;
D
=0
parameter:
t
p
1
10 µs
100 µs
1 ms
1 µs
4 Max. transient thermal impedance
Z
thJA
=f(t
p
)
parameter:
D
=t
p
/T
10
3
0.1
10 ms
DC
Z
thJA
[K/W]
0.5
I
D
[A]
0.01
10
2
0.2
0.1
0.001
0.05
0.02
0.01
single pulse
0.0001
0.1
1
10
100
1000
10
1
0.0001
0.001
0.01
0.1
1
10
100
V
DS
[V]
t
p
[s]
Rev 2.1
page 4
2012-05-10
BSS119N
5 Typ. output characteristics
I
D
=f(V
DS
);
T
j
=25 °C
parameter:
V
GS
0.8
10 V
4.5 V
6 Typ. drain-source on resistance
R
DS(on)
=f(I
D
);
T
j
=25 °C
parameter:
V
GS
10000
9000
8000
3V
3.3 V
3.5 V
4V
0.6
4V
7000
0.4
3.5 V
R
DS(on)
[mW]
6000
5000
4000
4.5 V
I
D
[A]
0.2
3.3 V
3000
2000
5V
10 V
3V
2.8 V
1000
0
0
0
2
4
6
8
10
0
0.2
0.4
0.6
0.8
V
DS
[V]
I
D
[A]
7 Typ. transfer characteristics
I
D
=f(V
GS
); |V
DS
|>2|I
D
|R
DS(on)max
8 Typ. forward transconductance
g
fs
=f(I
D
);
T
j
=25 °C
0.8
0.8
0.7
0.6
25 °C
150 °C
0.6
0.5
0.4
g
fs
[S]
0
1
2
3
4
5
I
D
[A]
0.4
0.3
0.2
0.2
0.1
0
0
0.0
0.2
0.4
0.6
0.8
V
GS
[V]
I
D
[A]
Rev 2.1
page 5
2012-05-10
FPGA/CPLD
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