Data Sheet AS1500/1/2/3
Digital Potentiometer
AS1500/AS1501/AS1502/AS1503
Key Features
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DATASHEET
PRELIMINARY FACT SHEET
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256-Position
Available in four Resistance values
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AS1500 resistance 10kOhms
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AS1501 resistance 20kOhms
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AS1502 resistance 50kOhms
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AS1503 resistance 100kOhms
Power Shutdown —Less than 1 µA
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
2.7 V to 5.5 V Single-Supply Operation
Temperature Range –40°C to +125°C
Package SO-8
Compatible to AD8400
programming rates up to 10MHz. The AS1500 is available in
four different resistor values. The AS1500 incorporates a
10kΩ, the AS1501 a 20kΩ, the AS1502 a 50kΩ and the
AS1503 a 100kΩ fixed resistor. The wiper contact taps the
fixed resistor at points determined by the 8-bit digital code
word. The resistance between the wiper and the endpoint of
the resistor is linear. The switching action is performed in a
way that no glitches occur. Furthermore the AS150x product
family includes a shutdown mode, where it consumes less
than 1µA. The AS150x is available in an 8-pin SOIC
package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +125°C.
Applications
General Description
The AS1500 is a digital potentiometer with 256
programmable steps. The values of the resistor can be
controlled via 3 wire serial interface capable to handle
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Line Impedance Matching
Volume Control, Panning
Mechanical Potentiometer Replacement
Power Supply Adjustment
Programmable Filters, Delays, Time Constants
VDD
B 1
GND 2
CSN 3
SDI
4
8
A
W
VDD
CK
AS150x
Top View
SDI
CK
CSN
A
10 Bit
Serial
Latch
8
8-Bit
Latch
8
W
B
7
6
5
AS1500
GND
Figure 1
Pinout andfunctional Block Diagram of Digital Potentiometer AS150x family
Revision 1.0, Oct 2004
Page 1 of 8
Data Sheet AS1500/1/2/3
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted.)
Parameter
VDD to GND
VA, VB, VW to GND
AX – BX, AX – WX, BX – WX
Digital Input and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJ max)
Storage Temperature
Package body temperature
1
Package Power Dissipation
ESD
2
Limits
–0.3V, +7V
0V, VDD
±20mA
0V, +7V
–40°C to +125°C
150°C
–65°C to +150°C
260°C
(TJ max – TA) /
θJA
1kV
Table 1: Absolute Maximum Ratings
Pin
1
2
3
4
5
6
7
8
Table
Description
Terminal B RDAC
Ground
Chip Select Input, Active Low. When CS returns high,
CSN
data in the serial input register is loaded into the DAC
register.
SDI
Serial Data Input
CK
Serial Clock Input, Positive Edge Triggered.
Positive power supply, specified for operation at both 3V
VDD
and 5V.
W
Wiper RDAC
A
Terminal A RDAC
2: Pin Function Description
Name
B
GND
1
2
The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity
Classification for non hermetic Solid State Surface Mount Devices”.
HBM MIL-Std883E 3015.7methods.
Page 2 of 8
Revision 1.0, Oct 2004
Data Sheet AS1500/1/2/3
AS1500 / AS1501 – SPECIFICATIONS
VDD = 3V±10% or 5V±10%, V
A
= VDD, V
B
= 0V, –40°C
≤
T
A
≤
+125°C unless otherwise noted.
ELECTRICAL CHARACTERISTICS – 10k and 20k VERSIONS
Parameter
Symbol Conditions
DC CHARACTERISTICS RHEOSTAT MODE
T
A
= 25°C, VDD = 5V, AS1500, Version: 10kΩ
Nominal Resistance
4
R
AB
T
A
= 25°C, VDD = 5V, AS1501, Version: 20kΩ
5
Resistance Tempco
∆R
AB
/∆T V
AB
= VDD, Wiper = No Connect
Wiper Resistance
R
W
VDD = 5V
6
Resistor Differential NL
R-DNL R
WB
, VDD = 5V, V
A
= No Connect
Resistor Integral NL
R-INL
R
WB
, VDD = 5V, V
A
= No Connect
DC CHARACTERISTICS POTENTIOMETER DIVIDER
Resolution
N
VDD = 5.5V T
A
= 25°C
Integral Nonlinearity
INL
VDD = 2.7V T
A
= 25°C
VDD = 5.5V T
A
= 25°C
Differential Nonlinearity
DNL
VDD = 2.7V T
A
= 25°C
Voltage Divider Tempco
∆V
W
/∆T Code = 80
H
Full-Scale Error
V
WFSE
Code = FF
H
, VDD = 5.5V
Zero-Scale Error
V
WZSE
Code = 00
H
, VDD = 5.5V
RESISTOR TERMINALS
Voltage Range
7
V
A, B, W
8
Ax, Bx
Capacitance
C
A, B
f =1MHz, Measured to GND, Code = 80
H
Capacitance Wx
C
W
f =1MHz, Measured to GND, Code = 80
H
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
VDD = 5V
Input Logic Low
V
IL
VDD = 5V
Input Logic High
V
IH
VDD = 3V
Input Logic Low
V
IL
VDD = 3V
Input Current
I
IH
, I
IL
V
IN
= 5V or 0V, VDD = 5V
Input Capacitance
C
IL
POWER SUPPLIES
Power Supply Range
VDD
Supply Current (CMOS)
IDD
V
IH
= VDD or V
IL
= 0V, VDD = 5.5V
9
Supply Current (TTL)
IDD
V
IH
= 2.4V or 0.8V, VDD = 5.5V
Power Dissipation
P
DISS
V
IH
= VDD or V
IL
= 0V, VDD = 5.5V
(CMOS)
10
AS1500, Version: 10kΩ
Power Supply Suppression
VDD = 5V + 0.5V
P
PSSR
sine wave @ 1kHz
Ratio
AS1501, Version: 20kΩ
11
DYNAMIC CHARACTERISTICS
BW_10k R
WB
= 10kΩ, VDD = 5V
Bandwidth –3dB
Bandwidth –3dB
BW_20k R
WB
= 20kΩ, VDD = 5V
Total Harmonic Distortion
THD
W
V
A
= 1V
RMS
+ 2V
DC
, V
B
= 2V
DC
, f = 1kHz
R
WB
= 5kΩ, V
A
= VDD, V
B
= 0V, ±1% Error
t
S
_10k
Band
V
W
Settling Time
R
WB
= 10kΩ, V
A
= VDD, V
B
= 0V, ±1% Error
t
S
_20k
Band
e
NWB
_10k R
WB
= 5kΩ, f =1kHz
Resistor Noise Voltage
e
NWB
_20k R
WB
= 10kΩ, f =1kHz
Table 3: Electrical Characteristics – 10k and 20k Versions
Min
8
16
20
–1
–2
–2
–2
–1
–1
–4
0
0
Typ
3
10
20
500
100
±1/4
±1/2
8
±1/2
±1/2
±1/4
±1/4
15
–2.8
1.3
75
120
Max
12
24
200
+1
+2
+2
+2
+1
+1
0
2
VDD
Unit
kΩ
kΩ
ppm/°C
Ω
LSB
LSB
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
V
V
V
V
µA
pF
V
µA
mA
µW
dB
dB
kHz
kHz
%
µs
µs
nV/
√
Hz
nV/
√
Hz
2.4
0.8
2.1
0.6
±1
5
2.7
0.1
0.9
-54
-52
1000
500
0.003
2
4
9
13
5.5
1
4
27.5
-25
-25
3
Typicals represent average readings at 25°C and VDD = 5V.
4
Wiper is not connected. I
AB
= 350µA for the 10kΩ version and 175µA for the 20kΩ version.
5
All Tempcos are guaranteed by design and not subject to production test.
6
Terminal A is not connected. I
W
= 350µA for the 10kΩ version and 175µA for the 20kΩ version.
7
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8
All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5V
bias on the measured terminal. The remaining resistor terminals are left open circuit.
9
Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.
10
P
DI SS
is calculated from (IDD×VDD). CMOS logic level inputs result in minimum power dissipation.
11
All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VDD=5V.
Revision 1.0, Oct 2004
Page 3 of 8
Data Sheet AS1500/1/2/3
AS1502 / AS1503 – SPECIFICATIONS
VDD = 3V±10% or 5V±10%, V
A
= VDD, V
B
= 0V, –40°C
≤
T
A
≤
+125°C unless otherwise noted.
ELECTRICAL CHARACTERISTICS – 50k and 100k VERSIONS
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE
T
A
= 25°C, VDD = 5V, AS1502, Version: 50kΩ
Nominal Resistance
13
R
AB
T
A
= 25°C, VDD = 5V, AS1503, Version: 100kΩ
14
Resistance Tempco
∆R
AB
/∆T V
AB
= VDD, Wiper = No Connect
Wiper Resistance
R
W
VDD = 5V
Resistor Differential NL
15
R-DNL R
WB
, VDD = 5V, V
A
= No Connect
Resistor Integral NL
R-INL
R
WB
, VDD = 5V, V
A
= No Connect
DC CHARACTERISTICS POTENTIOMETER DIVIDER
Resolution
N
VDD = 5.5V T
A
= 25°C
Integral Nonlinearity
INL
VDD = 2.7V T
A
= 25°C
VDD = 5.5V T
A
= 25°C
Differential Nonlinearity
DNL
VDD = 2.7V T
A
= 25°C
Voltage Divider Tempco
∆V
W
/∆T Code = 80
H
Full-Scale Error
V
WFSE
Code = FF
H
, VDD = 5.5V
Zero-Scale Error
V
WZSE
Code = 00
H
, VDD = 5.5V
RESISTOR TERMINALS
Voltage Range
16
V
A, B, W
17
Ax, Bx
Capacitance
C
A, B
f = 1MHz, Measured to GND, Code = 80
H
Capacitance Wx
C
W
f = 1MHz, Measured to GND, Code = 80
H
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
VDD = 5V
Input Logic Low
V
IL
VDD = 5V
Input Logic High
V
IH
VDD = 3V
Input Logic Low
V
IL
VDD = 3V
Input Current
I
IH
, I
IL
V
IN
= 5V or 0V, VDD = 5V
Input Capacitance
C
IL
POWER SUPPLIES
Power Supply Range
VDD
Supply Current (CMOS)
IDD
V
IH
= VDD or V
IL
= 0V, VDD = 5.5V
18
Supply Current (TTL)
IDD
V
IH
= 2.4V or 0.8V, VDD = 5.5V
Power Dissipation
P
DISS
V
IH
= VDD or V
IL
= 0V, VDD = 5.5V
(CMOS)
19
AS1502, Version: 50kΩ
Power Supply Suppression
VDD = 5V + 0.5V
P
PSSR
AS1503, Version:
sine wave @ 1kHz
Ratio
100kΩ
DYNAMIC CHARACTERISTICS
20
BW_50k R
WB
= 50kΩ, VDD = 5V
Bandwidth –3dB
Bandwidth –3dB
BW_100k R
WB
= 100kΩ, VDD = 5V
Total Harmonic Distortion
THD
W
V
A
= 1V
RMS
+ 2V
DC
, V
B
= 2V
DC
, f = 1kHz
R
WB
= 50kΩ, V
A
= VDD, V
B
= 0V, ±1% Error
t
S
_50k
Band
V
W
Settling Time
R
WB
= 100kΩ, V
A
= VDD, V
B
= 0V, ±1% Error
t
S
_100k
Band
e
NWB
_50k R
WB
= 50kΩ, f = 1kHz
Resistor Noise Voltage
e
NWB
_100
R
WB
= 100kΩ, f = 1kHz
k
Table 4: Electrical Characteristics – 50k and 100k Versions
Min
40
80
20
–1
–2
–4
–4
–1
–1
–1
0
0
Typ
12
50
100
500
100
±1/4
±1/2
8
±1
±1
±1/4
±1/4
15
–0.25
0.1
15
80
Max
60
120
200
+1
+2
+4
+4
+1
+1
0
1
VDD
Unit
kΩ
kΩ
ppm/°C
Ω
LSB
LSB
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
V
V
V
V
µA
pF
V
µA
mA
µW
dB
dB
kHz
kHz
%
µs
µs
nV/
√
Hz
nV/
√
Hz
2.4
0.8
2.1
0.6
±1
5
2.7
0.1
0.9
-43
-48
220
110
0.003
9
18
20
29
5.5
1
4
27.5
tbd.
tbd.
Typicals represent average readings at 25°C and VDD = 5V.
Wiper is not connected. I
AB
= 70µA for the 50kΩ version and 35µA for the 100kΩ version.
14
All Tempcos are guaranteed by design and not subject to production test.
15
Terminal A is not connected. I
W
= 70µA for the 50kΩ version and 35µA for the 100kΩ version.
16
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
17
All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5V
bias on the measured terminal. The remaining resistor terminals are left open circuit.
18
Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.
19
P
DI SS
is calculated from (IDD×VDD). CMOS logic level inputs result in minimum power dissipation.
20
All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VDD=5V.
12
13
Revision 1.0, Oct 2004
Page 4 of 8
Data Sheet AS1500/1/2/3
AS150x – SPECIFICATIONS
(VDD = 3V±10% or 5V±10%, VA = VDD, VB = 0V,
–40°C≤TA≤+125°C unless otherwise noted.)
CK
SD
1
0
1
0
1
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ELECTRICAL CHARACTERISTICS–ALL
VERSIONS
Sym-
Typ
Conditions Min
21
Max Unit
bol
SWITCHING CHARACTERISTICS
22, 23
Input Clock
Clock Level
t
CH
, t
CL
50
ns
Pulsewidth
High or Low
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CSN Setup Time
t
CSS
10
ns
CSN High
10
ns
t
CSW
Pulsewidth
CK Fall to CSN Rise
t
CSH
0
ns
Hold Time
CSN Rise to Clock
10
ns
t
CS1
Rise Setup
Parameter
Table 5: Switching Characteristics
DAC Register
CS
VD
V
O UT
0V
Figure 2: Timing Diagram
SDI
1
0
1
0
1
0
A
X
or
t
C
A
X
or
t
D
t
D
t
CS
t
CL
CK
t
CS
CSN
t
CS
t
CS
t
S
±1%
±1% Error
V
O UT
0V
V
DD
Detailed Description
Serial-Programming
Programming of the AS150x is done via the 3 wire serial
interface. The three input signals are serial data input
(SDI), clock(CK) and chip select (CS). A programming
sequence consists of 10-bit, where the last eight bit
contain the code word for the resistor value. The first two
bits A1 and A0 have to be low(see Table ). The data is
shifted into the internal 10 Bit register with the rising edge
of the CK signal. With the rising edge of the CSN signal
the data becomes valid and the resistance is updated (see
figure 2). A detailed block diagram is shown in figure 3.
A1 A0 D7
0
0 MSB
D6
D5
D4
D3
Data
D2
D1
D0
LSB
Figure 3: Detailed Timing Diagram
Rheostat Operation
The digital potentiometer family AS150x offers nominal
resistor values of 10kΩ, 20 kΩ, 50kΩ and 100kΩ. The
resistor has 256 contact points where the wiper can access
the resistor. The 8-bit code word determines the position
of the wiper and is decoded through an internal logic. The
lowest code 00h is related to the terminal B. The
resistance is then only determined by the wiper resistance
(100Ω). The resistance for the next code 01h is the
nominal resistor RAB (10kΩ, 20 kΩ, 50kΩ or 100kΩ)
divided through 256 plus the wiper resistor. In case of
AS1501 (10kΩ) the total resistance is 39Ω+100Ω=139Ω.
Accordingly the resistor for code 02h is 78Ω+100Ω=178Ω.
The last code 255h does not connect to terminal A directly
(see Figure 5). So the maximum value is 10000Ω - 39Ω
+100Ω = 10061Ω. The general formula for the calculation
of the resistance R
WB
is:
R
WB
(Dx)= (Dx)/256⋅R
AB
+ R
W
Table 6: Serial data format (16 bits)
21
22
23
Typicals represent average readings at 25°C and VDD=5V.
Guaranteed by design and not subject to production test.
Resistor-terminal capacitance tests are measured with 2.5V
bias on the measured terminal. The remaining resistor
terminals are left open circuit.
See timing diagram for location of measured values. All input
control voltages are specified with t
R
= t
F
= 1ns (10% to 90% of
VDD) and timed from a voltage level of 1.6V. Switching
characteristics are measured using VDD=3V or 5V. To avoid
false clocking, a minimum input logic slew rate of 1V/µs should
be maintained.
where R
AB
is the nominal resistance between terminal A
and B, R
W
is the wiper resistance and D
X
is the 8-Bit Code
word. In Table 7 the resistor values between the wiper and
terminal B for AS1501 are given for specific codes D
X
. In
the zero-scale condition the wiper resistance of 100Ω
remains present.
Revision 1.0, Oct 2004
Page 5 of 8
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