APW7035
Advanced PWM and Linear Power Control
Features
•
2 Regulated Voltage are provided
General Description
The APW7035 integrates PWM controller and linear
controller , as well as the monitoring and protection
functions into a single package , which provides two
controlled power outputs with over-voltage and over-
current protections. The PWM controller regulates
the DDR reference voltage (1.25V) or GPU Voltage
(2.05V) with a synchronous-rectified buck converter.
The linear controller regulates power for Memory
Voltage.
The precision reference and voltage-mode PWM
control provide
±1%
static regulation. The linear con-
troller drives an external N-channel MOSFET to pro-
vide adjustable voltage.
The APW7035 monitors all the output voltages , and
a single Power Good signal is issued when the PWM
Voltage is within
±10%
of the DAC setting and the
Linear regulator output levels are above their under-
voltage thresholds. Additional built-in over-voltage pro-
tection for the PWM output uses the lower MOSFET
to prevent output voltages above 115% of the DAC
setting. The PWM over-current function monitors the
output current by using the voltage drop across the
upper MOSFET’s R
DS(ON)
, eliminating the need for a
current sensing resistor.
The APW7035A/B/C/D support a TTL 3-input Digital
to Analog converter that adjusts the synchronous-
rectified buck converter output from 1.00V to 3.20V
, reference to Table1.
−
Switching Power for Fixed Voltage (1.25V /
2.05V) or Adjustable Voltage
−
Linear Regulator for FBVDDQ(2.5V)
•
•
Simple Single-Loop Control Design
−
Voltage-Mode PWM Control
Excellent Output Voltage Regulation
−
PWM Output : ±1%
−
Linear Output : ±3%
•
Fast Transient Response
−
High-Bandwidth Error Amplifier
−
Full 0% to 100% Duty Ratio
•
•
•
Power-Good Output Voltage Monitor
Over-Voltage and Over-Current Fault Monitors
Small Converter Size
−
Constant Frequency Operation(200kHz)
−
Reduce External Component Count
Applications
•
•
•
•
Motherboard Power Regulation for Computers
Low-Voltage Distributed Power Supplies
VGA Card Power Regulation
Termination Voltage
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
1
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APW7035
Pin Description
VCC
DRIVE
NC
NC
PGOOD
SD
VSEN2
SS
NC
VAUX
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
UGATE
PHASE
LGATE
PGND
OCSET
VSEN1
FB
COMP
NC
GND
VCC
DRIVE
VID2
VID1
VID0
SD
VSEN2
SS
NC
VAUX
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
UGATE
PHASE
LGATE
PGND
OCSET
VSEN1
FB
COMP
NC
GND
APW7035-12/19
APW7035A/B/C/D
Ordering Information
A P W 703 5
L ea d F re e C o de
H a nd ling C od e
T e m p . R an ge
P a c ka ge C od e
V o ltag e C o de
V o ltag e C o de
12 : 1.2 5V
2 0 : 2.05 V
A : 1 .0 0V ~1 .35 V
B : 1 .40 V ~ 1.75 V C : 1 .8 0V ~2 .40 V D : 2 .5 0V ~3 .20 V
P a c ka ge C od e
K : S O P -2 0
T e m p . R an ge
C : 0 to 70
°
C
H a nd ling C od e
T U : T u be
T R : T ap e & R ee l
L ea d F re e C o de
L : L ea d F re e D evice
B lan k : O rigina l D evice
Block Diagram
VSEN2
VAUX
VSEN1
OCSET
VCC
´
1.10
+
´
0.75
+
-
1.5V
´
1.15
+
-
INHIBIT
SOFT
START &
FAULT
LOGIC
V
CC
+
2 8m A
SS
DAC
ERROR
AMP1
-
+
-
PWM
COMP1
PWM1
4.5V
+
-
V
DAC
DRIVE
-
-
+
+
-
2 0 0m A
Power-on
Reset (POR)
VAUX
´
0.90
+
-
PGOOD
VCC
OV
OC1
UGATE
+
-
INHIBIT
GATE
CONTROL
PHASE
SD
V
CC
LGATE
PGND
GND
DAC
+
-
OSCILLATOR
SYNCH
DRIVE
VID0 VID1 VID2
FB
COMP
Copyright
ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
2
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APW7035
Absolute Maximum Ratings
Symbol
V
CC
V
I
, V
O
T
A
T
J
T
STG
T
S
Supply Voltage
Input , Output or I/O Voltage
Operating Ambient Temperature Range
Junction Temperature Range
Storage Temperature Range
Soldering Temperature
Parameter
Rating
15
GND -0.3 V to V
CC
+0.3
0 to 70
0 to 125
-65 to +150
300 ,10 seconds
Unit
V
V
°C
°C
°C
°C
Thermal Characteristics
Symbol
R
θJA
Parameter
Thermal Resistance in Free Air
SOIC
SOIC (with 3in
2
of Copper)
Value
75
65
Unit
°C/W
Electrical Characteristics
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic.
APW7035
Min. Typ. Max.
9
Unit
Symbol
V
CC
Supply Current
I
CC
Parameter
Test Conditions
UGATE, LGATE, DRIVE
open
Vocset=4.5V
Vocset=4.5V
Vocset=4.5V
Vocset=4.5V
Nominal Supply Current
mA
Power-on Reset
Rising VCC Threshold
Falling VCC Threshold
Rising VAUX Threshold
VAUX Threshold Hysteresis
Rising V
OCSET
Threshold
Oscillator
F
OCS
∆V
OSC
Free Running Frequency
Ramp Amplitude
RT= Open
RT= Open
185
200
1.9
215
kHz
V
P-P
10.7
8.2
2.5
0.5
1.26
V
V
V
V
V
Copyright
ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
3
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APW7035
Electrical Characteristics Cont.
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic.
APW7035
Min. Typ. Max.
-1.0
1.265
-2.5
3
40
88
15
6
1
3.5
1
3
115
170
200
28
109
93
2
0.8
120
230
+2.5
+1.0
Unit
Symbol
Parameter
Test Conditions
DAC and Bandgap Reference
V
DAC
DACOUT Voltage accuracy
V
BG
Bandgap Reference Voltage
Bandgap Reference Tolerance
Linear Regulators
Regulation
Output Drive Current
VAUX-V
DRIVE
>0.6V
Synchronous PWM Controller Error Amplifier
DC Gain
GBWP Gain-Bandwidth Product
SR
Slew Rate
COMP=10pF
PWM Controller Gate Driver
I
UGATE
UGATE Source
V
CC
=12V, V
UGATE
=6V
R
UGATE
UGATE Sink
V
UGATE1-PHASE
=1V
I
LGATE
LGATE Source
V
CC
=12V, V
LGATE
=1V
R
LGATE
LGATE Sink
V
LGATE
= 1V
Protection
VSEN1 Over-Voltage
VSEN1 Rising
Protection
I
OCSET
OCSET Current Source
V
OCSET
= 4.5V
DC
I
SS
Soft Start Current
Power Good
VSEN1 Upper Threshold
VSEN1 Rising
VSEN1 Under Voltage
VSEN1 Rising
VSEN1 Hysteresis
Upper /Lower Threshold
V
PGOOD
PGOOD Voltage Low
I
PGOOD
= -4mA
%
V
%
%
mA
dB
MHz
V/µs
A
Ω
A
Ω
%
µA
µA
%
%
%
V
20
Functional Pin Description
VCC (Pin 1)
Provide a 12V bias supply for the IC to this pin. This
pin also provides the gate bias charge for all the
MOSFETs controlled by the IC. The voltage at this
pin is monitored for Power-On Reset (POR) purposes.
DRIVE (Pin 2)
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the FBVDDQ
regulator’s pass transistor.
Copyright
ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
4
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APW7035
Functional Pin Description cont.
NC (Pin 3, Pin 4 and Pin 5)
No Connect. (APW7035-12,19)
PGOOD (Pin 5)
PGOOD is an open drain output used to indicate the
status of the output voltages. This pin is pulled low
when the synchronous regulator output is not within
±
10% of the DAC reference voltage or Linear regula-
tor outputs are below under-voltage thresholds.
(APW7035-A,B,C,D)
VID2 , VID1 , VID0 (Pin 3,4 and 5)
VID0-2 are the TTL-compatible input pins to the 3-bit
DAC. The logic states of these three pins program
the internal voltage reference (DAC). The level of DAC
sets the microprocessor core converter output volt-
age , as well as the corresponding PGOOD and OVP
thresholds. (APW7035-A,B,C,D)
SD (Pin 6)
The pin shuts down all the outputs. A TLL-compatible
, logic lebel high signal applied at this pin immedi-
ately discharges the soft-start capacitor , disbling all
the output.
VSEN2 (Pin 7)
Connect this pin to a resistor divider to set the linear
regulator (FBVDDQ) output voltage.
SS (Pin 8)
Connect a capacitor from this pin to ground. This
capacitor , along with an internal 28µA current source
, sets the soft-start interval of the converter.
NC (Pin 9 and Pin12)
No Connection.
VAUX (Pin 10)
This pin provides boost current for the linear regulator’s
output drives in the event bipolar NPN transistors
Copyright
ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
5
(instead of N-channel MOSFETs) are employed as
pass elements. The voltage at this pin is monitored
for power-on reset purposes.
GND (Pin 11)
Signal ground for the IC. All voltage levels are mea-
sured with respect to this pin.
FB and COMP (Pin 13, and 14)
COMP and FB are the available external pins of the
PWM converter error amplifier. The FB pin is the
inverting input of the error amplifier. Similarly , the
COMP pin is the error amplifier output. These pins
are used to compensate the voltage-mode control
feedback loop of the synchronous PWM converter.
VSEN1 (Pin 15)
This pin is connected to the PWM converter’s output
voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for
over- voltage
protection.
OCSET (Pin 16)
Connect a resistor from this pin to the drain of the
respective upper MOSFET. This resistor , an inter-
nal 200µA current source , and the upper MOSFET’s
on-resistance set the converter over-current trip point.
An over-current trip cycles the soft-start function. The
voltage at this pin is monitored for power-on reset
(POR) purposes and pulling this pin low with an open
drain device will shutdown the IC.
PGND (Pin 17)
This is the power ground connection. Tie the syn-
chronous PWM converter’s lower MOSFET source
to this pin.
LGATE (Pin 18)
Connect LGATE to the PWM converter’s lower
MOSFET gate. This pin provides the gate drive for
the lower MOSFET.
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