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DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
April 1984
Revised February 2000
DM74ALS109A
Dual J-K Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary Q and Q outputs.
Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the J, K input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K design allows operation as a D flip-flop by tying the
J and K inputs together.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
s
Improved AC performance over LS109 at approximately
half the power
Ordering Code:
Order Number
DM74ALS109AM
DM74ALS109AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CK
X
X
X
↑
↑
↑
↑
L
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
0
H
Q
0
Q
H
L
H (Note 1)
L
TOGGLE
Q
0
L
Q
0
Outputs
Q
L
H
H (Note 1)
H
L
=
LOW State
H
=
HIGH State
X
=
Don't Care
↑ =
Positive Edge Transition,
Q
0
=
Previous Condition of Q
Note 1:
This condition is nonstable; it will not persist when present and
clear inputs return to their inactive (HIGH) level. The output levels in this
condition are not guaranteed to meet the V
OH
specification.
© 2000 Fairchild Semiconductor Corporation
DS006196
www.fairchildsemi.com
DM74ALS109A
Logic Diagram
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2
DM74ALS109A
Absolute Maximum Ratings
(Note 2)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
82.5°C/W
111.5°C/W
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W(CLK)
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
Pulse Width
Clock HIGH
Clock LOW
Pulse Width (Note 3) Preset and Clear
Data Setup Time
(Note 3)
Data Hold Time
Free Air Operating Temperature
J or K
PRE or CLR inactive
0
14.5
14.5
15
15↑
10↑
0↑
0
70
ns
°C
Parameter
Min
4.5
2
0.8
−0.4
8
34
Nom
5
Max
5.5
Units
V
V
V
mA
mA
MHz
ns
ns
ns
ns
Note 3:
The (↑) arrow indicates the positive edge of the Clock is used for reference.
3
www.fairchildsemi.com
DM74ALS109A
Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25°C.
Symbol
V
IK
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
OH
= −400 µA
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V
V
IH
=
2V
V
CC
=
5.5V,
V
IH
=
7V
V
CC
=
5.5V,
V
IH
=
2.7V
V
CC
=
5.5V,
V
IL
=
0.4V
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V (Note 5)
I
OL
=
4 mA
I
OL
=
8 mA
I
I
Input Current at Max
Input Voltage
I
IH
High Level
Input Current
I
IL
Low Level
Input Current
I
O
(Note 4)
I
CC
Output Drive Current
Supply Current
Clock, J, K
Preset, Clear
Clock, J, K
Preset, Clear
Clock, J, K
Preset, Clear
−30
2.4
Conditions
V
CC
=
4.5V, I
I
= −18
mA
V
CC
−
2
0.25
0.35
0.4
0.5
0.1
mA
0.2
20
40
−0.2
−0.4
−112
4
mA
mA
mA
µA
Min
Typ
Max
−1.5
Units
V
V
V
V
Note 4:
The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, I
OS
.
Note 5:
I
CC
is measured with J, K, CLK and PRESET grounded, then with J, K, CLK and CLEAR grounded.
Switching Characteristics
over recommended operating free air temperature range
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Conditions
V
CC
=
4.5V to 5.5V
R
L
=
500Ω
C
L
=
50 pF
Preset or Clear
Q or Q
From
To
Min
34
3
13
Max
Units
MHz
ns
Preset or Clear
Q or Q
5
15
ns
Clock
Q or Q
5
16
ns
Clock
Q or Q
5
18
ns
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