Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
FEATURES
•
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model (C = 200pF, R = 0).
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed
D-type latch used in applications where two separate data paths
must be multiplexed onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing of
address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
CC
through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does
not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
•
Latch-up performance exceeds 500mA per JEDEC Standard
JESD-17.
•
Distributed V
CC
and GND pin configuration minimizes high-speed
switching noise.
•
Flow-through architecture optimizes PCB layout.
•
High-drive outputs (–32mA I
OH
, 64mA I
OL
).
•
74ABTH16260 incorporates bus-hold inputs which eliminate the
need for external pull-up resistors.
•
Package options:
–
56-pin plastic Shrink Small-Outline Package (SSOP)
–
56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nAx to nBx
nBx to nAx
C
L
= 50 pF
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
Outputs disabled
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL
2.8
2.5
4
6
100
ns
pF
pF
µA
UNIT
Input capacitance
Output capacitance
Total supply current
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16260 DL
74ABT16260 DGG
74ABTH16260 DL
74ABTH16260 DGG
NORTH AMERICA
BT16260 DL
BT16260 DGG
BH16260 DL
BH16260 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
1, 29, 56
2, 27, 30, 55
SYMBOL
An
1Bn
2Bn
OEA, OE1B, OE2B
LE1B, LE2B, LEA1B, LEA2B
FUNCTION
Data inputs/outputs (A)
Data inputs/outputs (B1)
Data inputs/outputs (B2)
Output enable input (active low)
Latch enable inputs
1998 Feb 10
2
853-2048-18945
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise specified)
1
LIMITS
SYMBOL
V
CC
V
I
V
O
I
O
I
IK
I
OK
T
stg
Supply voltage range
Input voltage range
Voltage range applied to any output in the high state or power-off state
Current into any output in the low state
Input clamp current
Output clamp current
Maximum power dissipation at T
amb
= 55°C (in still air)
Storage temperature range
V
I
< 0
V
O
< 0
see Note 3
–65
see Note 2
PARAMETER
CONDITIONS
MIN
–0.5
–0.5
–0.5
MAX
7
7
5.5
128
–18
–50
1.4
+150
UNIT
V
V
V
mA
mA
mA
W
°C
NOTES:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
RECOMMENDED OPERATING CONDITIONS
1
LIMITS
SYMBOL
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t∆/v
∆t∆/V
CC
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
Outputs enabled
200
–40
+85
0
PARAMETER
MIN
4.5
2
0.8
V
CC
–32
64
10
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
µs/V
°C
NOTE:
1. Unused or floating inputs must be held high or low.
1998 Feb 10
5
Embedded System
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