HIGH SPEED 36K (4K X 9)
SYNCHRONOUS
DUAL-PORT RAM
Features
◆
IDT70914S
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed clock-to-data output times
– Commercial: 12/15/20ns (max.)
Low-power operation
– IDT70914S
Active: 850 mW (typ.)
Standby: 50 mW (typ.)
Architecture based on Dual-Port RAM cells
– Allows full simultaneous access from both ports
Synchronous operation
– 4ns setup to clock, 1ns hold on all control, data, and address
inputs
– Data input, address, and control registers
– Fast 12ns clock to data out
– Self-timed write allows fast cycle times
– 16ns cycle times, 60MHz operation
Clock Enable feature
TTL-compatible, single 5V (+ 10%) power supply
Guaranteed data output hold times
Available in 68-pin PLCC, and 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
◆
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Functional Block Diagram
REGISTER
REGISTER
I/O
0-8L
WRITE
LOGIC
MEMOR
MEMORY
Y
ARRAY
ARRAY
WRITE
LOGIC
I/O
0-8R
SENSE
SENSE
AMPS DECODER DECODER AMPS
OE
L
CLK
L
CLKEN
L
Self-
timed
Write
Logic
REG
en
REG
en
OE
R
CLK
R
CLKEN
R
Self-
timed
Write
Logic
R/W
L
CE
L
REG
REG
R/W
R
CE
R
3490 drw 01
A
0L
-A
11L
A
0R
-A
11R
FEBUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-3490/11
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Description
The IDT70914 is a high-speed 4K x 9 bit synchronous Dual-Port
RAM. The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
provided by this approach allow systems to be designed with very short
cycle times. With an input data register, this device has been optimized for
applications having unidirectional data flow or bidirectional data flow in
bursts.
The IDT70914 utilizes a 9-bit wide data path to allow for parity at the
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
reception error checking.
Fabricated using CMOS high-performance technology, these Dual-
Ports typically operate on only 850mW of power at maximum high-speed
clock-to-data output times as fast as 12ns. An automatic power down
feature, controlled by
CE,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The IDT70914 is packaged in a 68-pin PLCC, and an 80-pin TQFP.
Pin Configurations
(1,2,3)
I/O
6L
I/O
7L
I/O
8L
GND
CE
L
N/C
N/C
R/W
L
V
CC
N/C
OE
L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
8
7
6
5
4
3
2
N/C
I/O
5L
V
CC
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
CC
I/O
4R
I/O
5R
70914
J68
(4)
1
68
67
66
65
64
63
62
61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CLKEN
L
CLK
L
CLK
R
CLKEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
6R
I/O
7R
I/O
8R
GND
CE
R
N/C
N/C
R/W
R
GND
GND
N/C
OE
R
A
11R
A
10R
A
9R
A
8R
A
7R
3490 drw 03
,
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
6.42
2
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Comme
Commercial Temperature Range
Pin Configuration
(1,2,3)
(con't.)
N/C
A
7R
A
8R
A
9R
A
10R
A
1
1R
N/C
OE
R
N/C
GND
GND
R/W
R
N/C
N/C
CE
R
GND
I/O
8R
I/O
7R
I/O
6R
N/C
N/C
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
CLKEN
R
CLK
R
CLK
L
CLKEN
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
N/C
N/C
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
9 10 11 12 13 14 15 16 17 18 19 20
70914
PN80
(4)
N/C
N/C
I/O
5R
I/O
4R
V
CC
I/O
3R
I/O
2R
I/O
1R
I/O
0R
GND
GND
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
V
CC
I/O
5L
N/C
N/C
N/C
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
N/C
OE
L
N/C
V
CC
R/W
L
N/C
N/C
CE
L
GND
I/O
8L
I/O
7L
I/O
6L
N/C
3
6.42
INDEX
3490 drw 04
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Commercial Temperature Range
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Terminal Voltage
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Com'l Only
-0.5 to +7.0
Unit
V
V
o
Maximum Operating Temperature
and Supply Voltage
(1,2)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
GND
0V
V
CC
5.0V
+
10%
3490 tbl 02
V
TERM
(2)
T
BIAS
T
STG
I
OUT
-0.5 to V
CC
-55 to +125
-65 to +150
50
C
C
NOTES:
1. This is the parameter T
A
. This is the "instant on" casae temperature
2. Industrial temperature: for specific speeds, packages and powers contact your
o
mA
3490 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3490 tbl 03
Capacitance
Symbol
C
IN
C
OUT
V
IH
V
IL
TQFP Only
(T
A
= +25°C, f = 1.0MH
z
)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
8
9
Unit
pF
pF
3490 tbl 04
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
CC
+ 10%.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
70914S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
10
10
0.4
___
Unit
µA
µA
V
V
3490 tbl 05
2.4
NOTE:
1. At V
CC
< 2.0V, input leakages are undefined
6.42
4
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Comme
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(4)
(V
CC
= 5V ± 10%)
70914S12
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby
Current (Both
Ports - All CMOS
Level Inputs)
Full Standby
Current (One
Port - All CMOS
Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(1)
CE
L
and
CE
R
= V
IH
f = f
MAX
(1)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs
Disabled, f=f
MAX
(1)
Both Ports
CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(3)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Disabled
f = f
MAX
(1)
Version
COM'L
Typ.
(2)
190
Max.
310
70914S15
Com'l Only
Typ.
(2)
180
Max.
300
Unit
mA
I
SB1
COM'L
95
150
90
140
mA
I
SB2
COM'L
170
220
160
210
mA
I
SB3
COM'L
10
15
10
15
mA
I
SB4
COM'L
165
210
155
200
mA
3490 tbl 06a
70914S20
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby
Current (Both
Ports - All CMOS
Level Inputs)
Full Standby
Current (One
Port - All CMOS
Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(1)
CE
L
and
CE
R
= V
IH
f = f
MAX
(1)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs
Disabled, f=f
MAX
(1)
Both Ports
CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(3)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Disabled
f = f
MAX
(1)
Version
COM'L
Typ.
(2)
170
Max.
290
Unit
mA
I
SB1
COM'L
85
130
mA
I
SB2
COM'L
150
200
mA
I
SB3
COM'L
10
15
mA
I
SB4
COM'L
145
190
mA
NOTES:
1. At f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input levels
of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, T
A
= 25°C for Typ, and are not production tested. I
CC DC
= 150mA (Typ)
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3490 tbl 06b
5
6.42
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