INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4511
BCD to 7-segment
latch/decoder/driver
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
FEATURES
•
Latch storage of BCD inputs
•
Blanking input
•
Lamp test input
•
Driving common cathode LED displays
•
Guaranteed 10 mA drive capability per output
•
Output capability: non-standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4511 are high-speed Si-gate CMOS
devices and are pin compatible with “4511” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4511 are BCD to 7-segment
latch/decoder/drivers with four address inputs (D
1
to D
4
),
an active LOW latch enable input (LE), an active LOW
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
APPLICATIONS
•
Driving LED displays
74HC/HCT4511
ripple blanking input (BI), an active LOW lamp test input
(LT), and seven active HIGH segment outputs (Q
a
to Q
g
).
When LE is LOW, the state of the segment outputs (Q
a
to
Q
g
) is determined by the data on D
1
to D
4
.
When LE goes HIGH, the last data present on D
1
to D
4
are
stored in the latches and the segment outputs remain
stable.
When LT is LOW, all the segment outputs are HIGH
independent of all other input conditions. With LT HIGH, a
LOW on BI forces all segment outputs LOW. The inputs LT
and BI do not affect the latch circuit.
•
Driving incandescent displays
•
Driving fluorescent displays
•
Driving LCD displays
•
Driving gas discharge displays
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
D
n
to Q
n
LE to Q
n
BI to Q
n
LT to Q
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
24
23
19
12
3.5
64
24
24
20
13
3.5
64
ns
ns
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
3
4
5
7, 1, 2, 6
8
13, 12, 11, 10, 9, 15, 14
16
SYMBOL
LT
BI
LE
D
1
to D
4
GND
Q
a
to Q
g
V
CC
NAME AND FUNCTION
lamp test input (active LOW)
ripple blanking input (active LOW)
latch enable input (active LOW)
BCD address inputs
ground (0 V)
segments outputs
positive supply voltage
74HC/HCT4511
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
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