EE PLD, 30ns, CMOS, CDIP24, CERDIP-24
| Parameter Name | Attribute value |
| Maker | Lattice |
| Parts packaging code | DIP |
| package instruction | DIP, |
| Contacts | 24 |
| Reach Compliance Code | unknown |
| ECCN code | EAR99 |
| Other features | 8 MACROCELLS; 1 EXTERNAL CLOCK; REGISTER PRELOAD; SHARED INPUT/CLOCK |
| maximum clock frequency | 22.2 MHz |
| JESD-30 code | R-GDIP-T24 |
| JESD-609 code | e0 |
| length | 31.875 mm |
| Dedicated input times | 12 |
| Number of I/O lines | 8 |
| Number of terminals | 24 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 12 DEDICATED INPUTS, 8 I/O |
| Output function | MACROCELL |
| Package body material | CERAMIC, GLASS-SEALED |
| encapsulated code | DIP |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Programmable logic type | EE PLD |
| propagation delay | 30 ns |
| Certification status | Not Qualified |
| Maximum seat height | 5.08 mm |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | TIN LEAD |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| width | 7.62 mm |
| Base Number Matches | 1 |
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