5962-8984001LA datasheet, PDF - EEWORLD Datasheet

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5962-8984001LA: DescriptionEE PLD, 25ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24; CategoryProgrammable logic Programmable logic devices; File Size675KB，22 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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5962-8984001LA Overview

EE PLD, 25ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24

5962-8984001LA Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	DIP
package instruction	DIP,
Contacts	24
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET
maximum clock frequency	25 MHz
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
length	31.9405 mm
Dedicated input times	12
Number of I/O lines	8
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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5962-8984001LA Related Products

	5962-8984001LA	5962-8984002LA	5962-8984003LA	5962-89840033A	5962-89840023A	5962-89840013A
Description	EE PLD, 25ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24	EE PLD, 20ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24	EE PLD, 15ns, CMOS, CDIP24, 0.250 X 1.250 INCH, SKINNY, CERAMIC, DIP-24	EE PLD, 15ns, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28	EE PLD, 20ns, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28	EE PLD, 25ns, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28
Parts packaging code	DIP	DIP	DIP	QLCC	QLCC	QLCC
package instruction	DIP,	DIP,	DIP,	QCCN,	QCCN,	QCCN,
Contacts	24	24	24	28	28	28
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET	PROGRAMMABLE OUTPUT POLARITY; 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET
maximum clock frequency	25 MHz	33.3 MHz	41.6 MHz	41.6 MHz	33.3 MHz	25 MHz
JESD-30 code	R-GDIP-T24	R-GDIP-T24	R-GDIP-T24	S-CQCC-N28	S-CQCC-N28	S-CQCC-N28
JESD-609 code	e0	e0	e0	e0	e0	e0
length	31.9405 mm	31.9405 mm	31.9405 mm	11.43 mm	11.43 mm	11.43 mm
Dedicated input times	12	12	12	12	12	12
Number of I/O lines	8	8	8	8	8	8
Number of terminals	24	24	24	28	28	28
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DIP	DIP	QCCN	QCCN	QCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	SQUARE
Package form	IN-LINE	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	25 ns	20 ns	15 ns	15 ns	20 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	5.08 mm	2.54 mm	2.54 mm	2.54 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	QUAD	QUAD	QUAD
width	7.62 mm	7.62 mm	7.62 mm	11.43 mm	11.43 mm	11.43 mm
Base Number Matches	1	1	1	1	1	1

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