530WA658M000DGR datasheet, PDF

Datasheet> All Categories > oscillator> 530WA658M000DGR

530WA658M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 658MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530WA658M000DGR Overview

CMOS/TTL Output Clock Oscillator, 658MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530WA658M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	658 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

In terms of energy storage, purchasing details of portable UPS power supply

Huamei brand BD-170 refrigerator circuit

Bipolar power circuit

Practical undervoltage and overvoltage protection circuit diagram

85——145V DC adjustable voltage stabilized power supply circuit diagram

555 "One control ten" miniature wireless remote control socket circuit

Ask a question: I recently saw a piece of news about the evaluation results of air purifiers on the market, by the China Household Electrical Appliances Research Institute. . . . [/size][/font][/backcolor][/color] Ba...; lidonglei1 Talking

Very good book: Very good book...; shulin RF/Wirelessly

modelsim simulation rom: The mif file data is stored in DEC format. Why can't the negative numbers stored in ROM be read out? When a negative number is read, the output is 0. Does anyone know?...; zhenpeng25 FPGA/CPLD

? Wireless data transmission and reception between arm and PC: The current situation is: the arm2440 development board and the PC are both equipped with wireless network cards. Through the router communication, the PC can ping the router and the arm. The arm runs...; hncb9431 ARM Technology

How is the stm32 mdk variable __IO u32 defined in the new mdk?: I'm using the new version of mdk, but the tutorial I downloaded for stm32 is the old version, so the definition doesn't match. Can the variable __IO u32 be replaced by u32? What does __io mean? [[i] T...; doganup MCU

Problems in developing vxworks bsp on Intel ATOM Zxx platform: I am a new student of embedded system. I am currently working on a project to develop vxworks bsp under Intel ATOM Zxx. I don't know which template is more suitable for modification? In other words, w...; omron88 Real-time operating system RTOS

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components