White Electronic Designs
PCMCIA SRAM Memory Card — SRA Series
SRAM MEMORY CARD 256KB THROUGH 8MB
FEATURES
High Performance SRAM memory Card
Single 5 Volt Supply
• (3.3V/5V operation is available as an option)
Fast Access times: 150ns
x8/x16 PCMCIA standard interface
Low Power CMOS technology provides very low
power and reliable data retention characteristics
• standby current < 100µA typical
Rechargeable Lithium battery with recharge circuitry
• eliminates the need for replaceable batteries
• standby current during recharge typically < 2mA
• battery backup time
– 7 months - type I card
– 18 months - type II card
typical based on 4MB (lower
densities will have greater storage
times)
Unlimited write cycles, no endurance issues
Optional Features:
• 2KB EEPROM attribute memory containing CIS
• Optional Hardware Write Protect switch
PC Card Standard Type I or Type II Form Factor
SRA01-SRA04
GENERAL DESCRIPTION
The WEDC SRAM Series (SRA) memory cards offer a
high performance nonvolatile storage solution for code
and data storage, disk caching, and write intensive mobile
and embedded applications.
Packaged in PCMCIA type I or type II housing (type II
for cards with extended battery backup time), the WEDC
SRAM SRA series is based on 1 or 4Mbit SRAM memories,
providing densities from 256 Kilobytes to 8 Megabytes.
The SRA series of SRAM memory cards requires a 5V
power supply and operates at speeds to 150ns. The cards
are based on advanced CMOS technology providing very
low power and reliable data retention characteristics.
WEDC’s SRAM cards contain a rechargeable lithium
battery and recharge circuitry, eliminating the need for
replaceable batteries found in many SRAM cards.
WEDC’s standard cards are shipped with WEDC’s SRAM
Logo. Cards are also available with blank housings
(no Logo). The blank housings are available in both a
recessed (for label) and flat housing. Please contact
WEDC sales representative for further information on
Custom artwork.
February 2002
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
BLOCK DIAGRAM
SRA01-SRA04
4MB SRAM Card Shown
[A1..A19]
address
buffer
SRAM
512K x 8
[A20..A22]
CSHi#
+ + + + +
CE1#
CE2#
WE#
OE#
REG#
A0
decoder
and
control
logic
CSLi#
CS-A#
RD#
RD#
WR# WR#
CTRL
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
CSHi#
[A1..A11]
S1
WP
Write Prot
Switch
VS1
VS2
GND
NC
NC
Vcc
CS-A#
RD#
WR#
ATTRIBUTE
MEMORY
CTRL
I/O BUFFER
[DO..D7]
[DO..D7]
[D8..D15]
+
BVD1
BVD2
Vcc
[D8..D15]
Power Management
and
Battery Control
Notes:
to internal
power
supply
1. pull down resistor (min 100k)
+
2. pull up resistor (min 10k)
Lithium Bat.
February 2002
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PINOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vppl
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
N.C.
N.C.
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
N.C.
Wait#
N.C.
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
SRA01-SRA04
LOW
LOW
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Active
LOW
LOW
N.C.
LOW
N.C.
N.C.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I
O
O
I/O
I/O
O
O
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
N.C.
N.C.
N.C.
Voltage Sense 2
Extended Bus Cycle
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
256KB(2)
512KB(2)
1MB(2)
2MB(2)
4MB(2)
N.C.
8MB(2,4)
N.C.
Low
Low
(3)
HIGH
LOW
Notes:
1. CD1# and CD2# are grounded internal to PC Card.
2. Shows density for which specified address bit is MSB. Higher order address bits are
no connects (i.e., 1MB A19 is MSB, A20 - A21 are NC).
3. BVD1 is an open drain output with a 10K ohm internal pull-up resistor.
4. Address bit 22 is used for the 8MB cards as well as the 6MB Cards.
February 2002
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PACKAGE DIMENSIONS
Type I
Interconnect area
1.6mm
± 0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
SRA01-SRA04
1.0mm ± 0.05
(0.039”)
Substrate area
54.0mm ± 0.10
(2.126”)
1.0mm ± 0.05
(0.039”)
85.6mm ± 0.20
(3.370”)
10.0mm MIN
(0.400”)
3.3mm ± T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
Type II
1.6mm
± 0.05
(0.063”)
1.0mm ± 0.05
(0.039”)
85.6mm ± 0.20
(3.370”)
3.0mm MIN
Substrate area
54.0mm ± 0.10
(2.126”)
1.0mm ± 0.05
(0.039”)
Interconnect area
10.0mm MIN
0.400”
5.0mm ± T1
(0.197”)
February 2002
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
CARD SIGNAL DESCRIPTION
Symbol
A0 - A25
Type
INPUT
Name and Function
SRA01-SRA04
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit. (address pins used are based on card density,see pinout
for highest used address pin)
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ0 - DQ7 constitute the lower
(even) byte and DQ8 - DQ15 the upper (odd) byte. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0,
CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7.
OUTPUT ENABLE:
Active low signal enabling read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Not used for SRAM cards
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are connected to ground internally on the
memory card. The host socket interface circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.
WRITE PROTECT:
Follows hardware Write Protect Switch. When Switch is placed in on position, signal is pulled high
(10K ohm). When switch is off signal is pulled low.
PROGRAM/ERASE POWER SUPPLY:
Not used for SRAM cards.
CARD POWER SUPPLY:
5.0V for all internal circuitry.
GROUND:
for all internal circuitry.
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY#
CD1#, CD2#
WP
VPP1, VPP2
V
CC
GND
REG#
RST
WAIT#
BVD1, BVD2
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT:
only used with cards built with optional attribute memory.
RESET:
Not used for SRAM cards
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
Provides status of Battery voltage.
BVD2 = BVD1 = V
OH
(battery voltage is guaranteed to retain data)
BVD2 = V
OL
, BVD1 = Voh (data is valid, battery recharge required)
BVD2 = BVD1 = V
OL
(data may no longer be valid, battery requires extended recharge)
VOLTAGE SENSE:
Notifies the host socket of the card’s VCC requirements. VS1 and VS2 are open to indicate a 5V,
16 bit card has been inserted.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left floating
VS1, VS2
RFU
N.C.
OUTPUT
FUNCTIONAL TRUTH TABLE
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
February 2002
Rev. 6
CE2# CE1#
H
H
H
L
H
L
L
L
L
H
H
H
H
L
L
H
L
L
L
H
A0 OE# WE#
X
X
X
L
L
H
H
L
H
X
L
H
X
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
REG#
X
H
H
H
H
X
H
H
H
H
Common Memory
D15-D8
D7-D0
High-Z
High-Z
High-Z
Even-Byte
High-Z
Odd-Byte
Odd-Byte
Even-Byte
Odd-Byte
High-Z
X
X
X
Odd-Byte
Odd-Byte
5
REG#
X
L
L
L
L
X
L
L
L
L
Attribute Memory
D15-D8
High-Z
High-Z
High-Z
Not Valid
Not Valid
X
X
X
X
X
D7-D0
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
X
Even-Byte
X
Even-Byte
X
X
Even-Byte
Odd-Byte
Even-Byte
X
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