530NC1281M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 530NC1281M00DG

530NC1281M00DG: DescriptionLVDS Output Clock Oscillator, 1281MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530NC1281M00DG Overview

LVDS Output Clock Oscillator, 1281MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530NC1281M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1281 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Photoelectric tracking control circuit

A tuned circuit composed of one-stage high-frequency amplification and one-stage frequency conversion

Simple intercom doorbell circuit

Feilu NSL-5 single-tube vertical electric heater circuit diagram

Acute coronary insufficiency alarm circuit

Thyristor test circuit

Problems with implementing SIP IME in wince: I have implemented an input method under SIP. There is a function button on my input method interface to exit the input method. Currently, I can hide the input method and return to the edit control of...; liguangemail Embedded System

Application of differential line pairs in high-speed PCB design: ...; 静若幽兰 PCB Design

Crystal oscillator issues: I use MSP430F1101. When the power supply voltage is 2.5V, I find that the program runs normally when using DCO, but when using an external 6MHz crystal, the OFIFG bit is not reset. I checked that the ...; wedh Microcontroller MCU

hfss18 version 3D image setting problem: How to display the color scale next to the 3D image after superimposing the model?...; 耩聴聴 TI Technology Forum

Doubts about the "edge detector" of the capture channel of the STM32 timer: How does the "edge detector" of the capture channel of the STM32 timer detect and identify edges? For example, if I want to detect the rising edge of a signal, what is the rising amplitude of my signa...; huixianfxt stm32/stm8

[BearPi-HM Nano, play Hongmeng "touch and pay"] -7-"pseudo touch and pay" LED control: [i=s]This post was last edited by sun63312 on 2021-8-16 13:30[/i]HarmonyOS " pseudo touch " LED control implementation 1. Introduction: It has been a long time since I started working on this project,...; sun63312 ARM Technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components