This product has been retired and is not available for designs. For new and current designs,
S29PL064J supersedes Am29PDL640G and is the factory-recommended migration path. Please refer
to the S29PL064J datasheet for specifications and ordering information. Availability of this document
is retained for reference and historical purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
26573
Revision
B
Amendment
+2
Issue Date
December 13, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29PDL640G
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Read/Write Flash Memory with Enhanced
VersatileIO
TM
Control
DISTINCTIVE CHARACTERISTICS
refer to the S29PL064J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
ARCHITECTURAL ADVANTAGES
64 Mbit Page Mode device
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.1 volt read, erase, and
program operations for battery-powered applications
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)
— Bank B: 24 Mbit (32 Kw x 48)
— Bank C: 24 Mbit (32 Kw x 48)
— Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
Enhanced VersatileI/O
TM
(V
IO
) Control
— Output voltage generated and input voltages tolerated
on all control inputs and I/Os is determined by the
voltage on the V
IO
pin
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
Both top and bottom boot blocks in one device
Manufactured on 0.17 µm process technology
20-year data retention at 125°C
Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 65 ns
Power consumption (typical values at 10 MHz)
— 25 mA active read current
— 15 mA program/erase current
— 0.2 µA typical standby mode current
This product has been retired and is not available for designs. For new and current designs, S29PL064J supersedes Am29PDL640G and is the factory-recommended migration path. Please
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV
families
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
WP#/ACC (Write Protect/Accelerate) input
— At V
IL
, protects the first and last two 4K word sectors,
regardless of sector protect/unprotect status
— At V
IH
, allows removal of sector protection
— At V
HH
, provides faster programming times in a factory
setting
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Package options
— 63-ball Fine-pitch BGA
— 80-ball Fine-pitch BGA
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
26573
Rev:
B
Amendment/+2
Issue Date:
December 13, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 4 Mwords. The device is offered in 63- or 80-ball
Fine-pitch BGA packages. The word-wide data (x16) ap-
pears on DQ15-DQ0. This device can be programmed
in-system or in standard EPROM programmers. A 12.0 V
V
PP
is not required for write or erase operations.
The device offers fast page access times of 25, 30, and 45
ns, with corresponding random access times of 65, 70, 85,
and 90 ns, respectively, allowing high speed microproces-
sors to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Bank
A
B
C
D
Sectors
8 Mbit (4 Kw x 8 and 32 Kw x 15)
24 Mbit (32 Kw x 48)
24 Mbit (32 Kw x 48)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
Page Mode Features
The device is AC timing, input/output, and package
compat-
ible with 4 Mbit x16 page mode mask ROM.
The page size
is 8 words.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V
to 3.1 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
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