This product has been retired and is not recommended for designs. For new and current designs,
S29GL064A supersedes Am29LV641G and is the factory-recommended migration path. Please refer
to the S29GL064A datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
June 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
25295
Revision
A
Amendment
+3
Issue Date
June 14, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am29LV641G
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O
™
Control
This product has been retired and is not recommended for designs. For new and current designs, S29GL064A supersedes Am29LV641G and is the factory-recommended migration path.
Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 2.7 to 3.6 volt read, erase, and program operations
■
SecSi
™
(Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
■
VersatileI/O
™
control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
■
Manufactured on 0.18 µm process technology
■
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash standard
■
Package options
— 48-pin TSOP and Reverse TSOP (LV641GH/L only)
— 63-ball Fine-Pitch BGA (LV640GU only)
— 64-ball Fortified BGA (LV640GU only)
■
Minimum 1 million erase cycle guarantee per sector
■
20-year data retention at 125
°
C
■
Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
■
Program and erase performance (V
HH
not applied to
the ACC input pin)
— Word program time: 7 µs typical
— Sector erase time: 0.6 s typical for each 32 Kword
sector
SOFTWARE AND HARDWARE FEATURES
■
Hardware features
—
Hardware reset input (RESET#):
resets device for
new operation
—
WP# input:
protects first or last 32 Kword sector
regardless of sector protection settings
(LV641GH/L only)
—
ACC input:
Accelerates programming time for higher
throughput during system production
■
Software features
—
Program Suspend & Resume:
read other sectors
before programming operation is completed
—
Sector Group Protection:
V
CC
-level method of
preventing program or erase operations within a
sector
—
Temporary Sector Group Unprotect:
V
ID
-level method
of changing in previously locked sectors
—
CFI (Common Flash Interface) compliant:
allows host
system to identify and accommodate multiple flash
devices
—
Erase Suspend/Erase Resume:
read/program other
sectors before an erase operation is complete
—
Data# Polling
and
toggle bits
provide erase and
programming operation status
—
Unlock Bypass Program
command reduces overall
multiple-word programming time
PERFORMANCE CHARCTERISTICS
■
High performance
— Access time ratings as fast as 55 ns
This document contains information on a product under development at Advance Micro Devices. The information is
intended to help you evaluate this product. Do not design in the product without contacting the factory. AMD reserves
the right to change or discontinue work on this proposed product without notice.
Publication#
25295
Rev:
A
Amendment/+3
Issue Date:
June 14, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV641G are 64 Mbit, 3.0 volt (3.0 V to 3.6 V)
single power supply flash memory devices organized
as 4,194,304 words. Data appears on DQ15–DQ0.
These devices are designed to be programmed in-sys-
tem with the standard system 3.0 volt V
CC
supply. A
12.0 volt V
PP
is not required for program or erase oper-
ations. The device can also be programmed in stan-
dard EPROM programmers.
Access times of 55 regulated volage and 70 ns full
voltage range are available for applications where V
IO
≥
V
CC
. The Am29LV641GH/L is offered in 48-pin
T S O P a n d r e v e r s e T S O P p a ck a g e s . T h e
Am29LV640GU is offered in a 63-ball Fine-pitch BGA
package, and a 64-ball Fortified BGA. To eliminate bus
contention each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
Each device requires only a
single 3.0 volt power
supply
(2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the V
IO
pin. This allows the device to operate in 1.8
V or 3 V system environment as required.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) or DQ6 (toggle)
status bits.
After a
program or erase cycle has been completed, the de-
5
vice is ready to read array data or accept another
command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved. The
Program Suspend/Program
Resume
feature enables the host system to pause a
program operation in a given sector to read any other
sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
SecSi
™
(Secured Silicon) Sector
provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming. (Am29LV641GH/L only)
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
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