Data Sheet No. PD60045-N
IR2103
(S)
HALF-BRIDGE DRIVER
Features
•
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout
3.3V, 5V and 15V logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
Internal set deadtime
High side output in phase with HIN input
Low side output out of phase with
LIN
input
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Deadtime (typ.)
600V max.
130 mA / 270 mA
10 - 20V
680 & 150 ns
520 ns
•
•
•
•
•
•
•
•
Packages
Description
The IR2103(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels. Proprietary HVIC
8-Lead SOIC
IR2103S
and latch immune CMOS technologies enable rug-
8-Lead PDIP
gedized monolithic construction. The logic input is
IR2103
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
V
CC
V
CC
HIN
LIN
V
B
HO
V
S
LO
TO
LOAD
HIN
LIN
COM
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IR2103
(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dVs/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage (HIN &
LIN
)
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 Lead PDIP)
(8 Lead SOIC)
(8 Lead PDIP)
(8 Lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
—
—
—
—
—
—
-55
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage (HIN &
LIN
)
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
0
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
125
Units
V
°C
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
2
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IR2103
(S)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF and T
A
= 25°C unless otherwise specified.
Symbol
ton
toff
tr
tf
DT
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Deadtime, LS turn-off to HS turn-on &
HS turn-on to LS turn-off
Delay matching, HS & LS turn-on/off
Min. Typ. Max. Units Test Conditions
—
—
—
—
400
—
680
150
100
50
520
—
820
220
170
90
650
60
ns
V
S
= 0V
V
S
= 600V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” (HIN) & Logic “0” (
LIN
) input voltage
Logic “0” (HIN) & Logic “1” (
LIN
) input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
supply undervoltage positive going
threshold
V
CC
supply undervoltage negative going
threshold
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
3
—
—
—
—
—
—
—
—
8
7.4
130
270
—
—
—
—
—
30
150
3
—
8.9
8.2
210
360
—
0.8
100
100
50
55
270
10
1
9.8
9
—
mA
—
V
µA
V
mV
V
CC
= 10V to 20V
V
CC
= 10V to 20V
I
O
= 0A
I
O
= 0A
V
B
= V
S
= 600V
V
IN
= 0V or 5V
V
IN
= 0V or 5V
HIN = 5V,
LIN
= 0V
HIN = 0V,
LIN
= 5V
V
O
= 0V, V
IN
= V
IH
PW
≤
10 µs
V
O
= 15V, V
IN
= V
IL
PW
≤
10 µs
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3
IR2103
(S)
Functional Block Diagram
V
B
Q
PULSE
FILTER
R
S
HO
DEAD
TIME
HIN
PULSE
GEN
UV
DETECT
HV
LEVEL
SHIFT
V
S
Vcc
V
CC
LIN
DEAD
TIME
LO
COM
Lead Definitions
Symbol Description
HIN
LIN
V
B
Logic input for high side gate driver output (HO), in phase
Logic input for low side gate driver output (LO), out of phase
High side floating supply
High side gate drive output
High side floating supply return
Low side and logic fixed supply
Low side gate drive output
Low side return
HO
V
S
V
CC
LO
COM
Lead Assignments
1
2
3
4
VCC
HIN
LIN
COM
VB
HO
VS
LO
8
7
6
5
1
2
3
4
VCC
HIN
LIN
COM
VB
HO
VS
LO
8
7
6
5
8 Lead PDIP
8 Lead SOIC
IR2103
4
IR2103S
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IR2103
(S)
HIN
LIN
50%
50%
LIN
ton
tr
90%
toff
90%
tf
HO
LO
LO
10%
10%
Figure 1. Input/Output Timing Diagram
50%
50%
HIN
ton
tr
90%
toff
90%
tf
HO
HIN
LIN
50%
50%
10%
10%
Figure 2. Switching Time Waveform Definitions
90%
HO
DT
10%
DT
LO
90%
10%
Figure 4. Deadtime Waveform Definitions
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