DM74S181N datasheet, PDF - EEWORLD Datasheet

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DM74S181N: DescriptionArithmetic Logic Unit, S Series, 4-Bit, TTL, PDIP24, PLASTIC, DIP-24; Categorylogic; File Size148KB，10 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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DM74S181N Overview

Arithmetic Logic Unit, S Series, 4-Bit, TTL, PDIP24, PLASTIC, DIP-24

DM74S181N Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	DIP,
Reach Compliance Code	unknown
Other features	CAPABLE OF 16 LOGIC & ARITHMETIC OPERATIONS; INTERNAL CARRY AND HIGHER ORDER LOOKAHEAD
series	S
JESD-30 code	R-PDIP-T24
length	31.915 mm
Logic integrated circuit type	ARITHMETIC LOGIC UNIT
Number of digits	4
Number of functions	1
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	30 ns
Maximum seat height	5.334 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Base Number Matches	1

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DM74S181 Arithmetic Logic Unit Function Generators

February 1992

DM74S181

Arithmetic Logic Unit Function Generators

General Description

These arithmetic logic units (ALU) function generators per-

form 16 binary arithmetic operations on two 4-bit words as

shown in Tables 1 and 2 These operations are selected by

the four function-select lines (S0 S1 S2 S3) and include

addition subtraction decrement and straight transfer

When performing arithmetic manipulations the internal car-

ries must be enabled by applying a low-level voltage to the

mode control input (M) A full carry look-ahead scheme is

available in these devices for fast simultaneous carry gen-

eration by means of two cascade-outputs (P and G) for the

four bits in the package When used in conjunction with the

DM74S182 full carry look-ahead circuits high-speed arith-

metic operations can be performed The typical addition

times shown below illustrate how little time is required for

addition of longer words when full carry look-ahead is em-

ployed The method of cascading 182 circuits with these

ALU’s to provide multi-level full carry look-ahead is illustrat-

ed under typical applications data for the DM74S182

(Continued)

Features

Arithmetic operating modes

Addition

Subtraction

Shift operand A one position

Magnitude comparison

Plus twelve other arithmetic operations

Logic function modes

EXCLUSIVE-OR

Comparator

AND NAND OR NOR

Plus ten other logic operations

Full look-ahead for high-speed operations on long

words

Connection Diagram

Dual-In-Line Package

Pin Designations

Designation

A3 A2 A1 A0

B3 B2 B1 B0

S3 S2 S1 S0

F3 F2 F1 F0

TL F 6473 – 1

Pin Nos

19 21 23 2

18 20 22 1

3 4 5 6

13 11 10 9

Function

Word A Inputs

Word B Inputs

Function-Select

Inputs

Inv Carry Input

Mode Control

Input

Function Outputs

Comparator Output

Carry Propagate

Output

Inv Carry Output

Carry Generate

Output

Supply Voltage

Ground

Order Number DM74S181N

See NS Package Number N24A

GND

1995 National Semiconductor Corporation

TL F 6473

RRD-B30M105 Printed in U S A

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