E2O0017-27-X2
¡ Semiconductor
MSM82C51A-2RS/GS/JS
¡ Semiconductor
This version: Jan. 1998
MSM82C51A-2RS/GS/JS
Previous version: Aug. 1996
UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
GENERAL DESCRIPTION
The MSM82C51A-2 is a USART (Universal Synchronous Asynchronous Receiver Transmitter)
for serial data communication.
As a peripheral device of a microcomputer system, the MSM82C51A-2 receives parallel data
from the CPU and transmits serial data after conversion. This device also receives serial data
from the outside and transmits parallel data to the CPU after conversion.
The MSM82C51A-2 configures a fully static circuit using silicon gate CMOS technology.
Therefore, it operates on extremely low power at 100
mA
(max) of standby current by
suspending all operations.
FEATURES
• Wide power supply voltage range from 3 V to 6 V
• Wide temperature range from –40°C to 85°C
• Synchronous communication upto 64 Kbaud
• Asynchronous communication upto 38.4 Kbaud
• Transmitting/receiving operations under double buffered configuration.
• Error detection (parity, overrun and framing)
• 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C51A-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C51A-2JS)
• 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C51A-2GS-K)
1/26
¡ Semiconductor
MSM82C51A-2RS/GS/JS
FUNCTIONAL BLOCK DIAGRAM
D
7 -
D
0
Data Bus
Buffer
Transmit
Buffer
(P - S)
TXD
DSR
DTR
CTS
RTS
Internal Bus Line
RESET
CLK
C/D
RD
WR
CS
Read/Write
Control
Logic
Transmit
Control
TXRDY
TXE
TXC
Modem
Control
Recieve
Buffer
(S - P)
RXD
Recieve
Control
RXRDY
RXC
SYNDET/BD
2/26
¡ Semiconductor
MSM82C51A-2RS/GS/JS
PIN CONFIGURATION (TOP VIEW)
28 pin Plastic DIP
D
2
D
3
RXD
GND
D
4
D
5
D
6
D
7
TXC
1
2
3
4
5
6
7
8
9
28 D
1
27 D
0
26 V
CC
25
RXC
24
DTR
23
RTS
22
DSR
21 RESET
20 CLK
19 TXD
18 TXEMPTY
17
CTS
16 SYNDET/BD
15 TXRDY
28 pin Plastic QFJ
4 GND
3 RXD
26 V
CC
27 D
0
2 D
3
1 D
2
28 D
1
WR
10
CS
11
C/D 12
RD
13
RXRDY 14
25
RXC
24
DTR
23
RTS
22
DSR
21 RESET
20 CLK
19 TXD
D
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
4
D
5
D
6
D
7
TXC
5
6
7
8
9
WR
10
CS
11
C/D 12
RD
13
RXRDY 14
TXRDY 15
SYNDET/BD 16
CTS
17
18
32 pin Plastic SSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D
1
D
0
V
CC
NC
RXC
DTR
RTS
DSR
RESET
CLK
TXD
TXEMPTY
NC
CTS
SYNDET/BD
TXRDY
D
3
RXD
NC
GND
D
4
D
5
D
6
D
7
TXC
WR
CS
NC
C/D
RD
RXRDY
TXEMPTY
3/26
¡ Semiconductor
MSM82C51A-2RS/GS/JS
FUNCTION
Outline
The MSM82C51A-2's functional configuration is programed by software.
Operation between the MSM82C51A-2 and a CPU is executed by program control. Table 1
shows the operation between a CPU and the device.
Table 1 Operation between MSM82C51A and CPU
CS
1
0
0
0
0
0
C/D
¥
¥
1
1
0
0
RD
¥
1
0
1
0
1
WR
¥
1
1
0
1
0
Data Bus 3-State
Data Bus 3-State
Status
Æ
CPU
Control Word
¨
CPU
Data
Æ
CPU
Data
¨
CPU
It is necessary to execute a function-setting sequence after resetting the MSM82C51A-2. Fig. 1
shows the function-setting sequence.
If the function was set, the device is ready to receive a command, thus enabling the transfer of
data by setting a necessary command, reading a status and reading/writing data.
External Reset
Internal Reset
Write Mode Instruction
Asynchronous
no
Write First Sync
Charactor
yes
Single
Sync Mode
no
Write Second Sync
Charactor
yes
End of Mode Setting
Fig. 1 Function-setting Sequence (Mode Instruction Sequence)
4/26
¡ Semiconductor
Control Words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
MSM82C51A-2RS/GS/JS
1) Mode Instruction
Mode instruction is used for setting the function of the MSM82C51A-2. Mode instruction
will be in “wait for write” at either internal reset or external reset. That is, the writing of a
control word after resetting will be recognized as a “mode instruction.”
Items set by mode instruction are as follows:
•
•
•
•
•
•
•
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)
Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters.
If sync characters were written, a function will be set because the writing of sync characters
constitutes part of mode instruction.
D
7
S
1
D
6
S
1
D
5
EP
D
4
PEN
D
3
L
2
D
2
L
1
D
1
B
2
D
0
B
1
Baud Rate Factor
0
0
Refer to
Fig. 3
SYNC
1
0
1
¥
0
1
16
¥
1
1
64
¥
Charactor Length
0
0
5 bits
1
0
6 bits
0
1
7 bits
1
1
8 bits
Parity Check
0
0
Disable
1
0
Odd
Parity
0
1
Disable
1
1
Even
Parity
Stop bit Length
0
0
Inhabit
1
0
1 bit
0
1
1.5 bits
1
1
2 bits
Fig. 2 Bit Configuration of Mode Instruction (Asynchronous)
5/26
京公网安备 11010802033920号
EEWORLD
