The HY57V56420H is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. HY57V56420H is organized as 4banks of 16,777,216x4.
HY57V56420H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
•
•
•
•
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
•
ORDERING INFORMATION
Part No.
HY57V56420HT-6
HY57V56420HT-K
HY57V56420HT-H
HY57V56420HT-8
HY57V56420HT-P
HY57V56420HT-S
HY57V56420HLT-6
HY57V56420HLT-K
HY57V56420HLT-H
HY57V56420HLT-8
HY57V56420HLT-P
HY57V56420HLT-S
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 16Mbits x 4
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.3/Nov. 01
1
HY57V56420H(L)T
PIN CONFIGURATION
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
54 pin TSOP II
400 mil x 875mil
0.8 mm pin pitch
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A12
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
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