This product has been retired and is not recommended for designs. For new and current designs,
S29AL032D supersedes Am29LV033C and is the factory-recommended migration path. Please refer
to the S29AL032D datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
22268
Revision
B
Amendment
+5
Issue Date
September 12, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV033C
32 Megabit (4 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29AL032D supersedes Am29LV033C and is the factory-recommended migration path.
Please refer to the S29AL032D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
SOFTWARE FEATURES
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■
Package options
— 63-ball FBGA
— 40-pin TSOP
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
Flexible sector architecture
— Sixty-four 64 Kbyte sectors
■
Manufactured on 0.32 µm process technology
PERFORMANCE CHARACTERISTICS
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming
in same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status
of program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■
ACC input pin
— Acceleration (ACC) function provides accelerated
program times
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data
in protected sectors in-system
■
Command sequence optimized for mass storage
— Specific addresses not required for unlock cycles
■
High performance
— Access times as fast as 70 ns
— Program time: 7 µs/byte typical utilizing Accelerate
function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million write cycles guaranteed
per sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22268
Rev:
B
Amendment/5
Issue Date:
September 12, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29LV033C is a 32 Mbit, 3.0 Volt-only Flash
memory organized as 4,194,304 bytes. The device is
offered in 63-ball FBGA and 40-pin TSOP packages.
The byte-wide (x8) data appears on DQ7–DQ0. All
read, program, and erase operations are accomplished
using only a single power supply. The device can also
be programmed in standard EPROM programmers.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle is
completed, the device is ready to read array data or
accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This is achieved in-system or via programming
equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read the boot-up firmware from the Flash
memory.
The device offers two power-saving features. When
addresses are stable for a specified amount of time,
the device enters the
automatic sleep mode.
The
system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29LV033C
22268B5 September 12, 2006
D A T A
S H E E T
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