Am29F200B
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21526
Revision
D
Amendment
4
Issue Date
Nobember 1, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 V for read and write operations
— Minimizes system level power requirements
■
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F200A device
■
High performance
— Access times as fast as 45 ns
■
Low power consumption
— 20 mA typical active read current (byte mode)
— 28 mA typical active read current for
(word mode)
— 30 mA typical program/erase current
— 1 µA typical standby current
■
Sector erase architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top or bottom boot block configurations available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 write/erase cycles guaranteed
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package options
— 44-pin SO
— 48-pin TSOP
— Known Good Die (KGD)
(see publication number 21257)
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■
Data# Polling and Toggle Bit
— Detects program or erase cycle completion
■
Ready/Busy# output (RY/BY#)
— Hardware method for detection of program or
erase cycle completion
■
Erase Suspend/Erase Resume
— Supports reading data from a sector not
being erased
■
Hardware RESET# pin
— Resets internal state machine to the reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21526
Rev:
D
Amendment:
4
Issue Date:
November 1, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The 8 bits of data appear on DQ0–DQ7; the 16 bits on
DQ0–DQ15. The Am29F200B is offered in 44-pin SO
and 48-pin TSOP packages. The device is also avail-
able in Known Good Die (KGD) form. For more
information, refer to publication number 21257. This
device is designed to be programmed in-system with
the standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for program or erase operations.
The device can also be reprogrammed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F200A, which was manufactured
using 0.5 µm process technology.
The standard device offers access times of 45, 50, 55,
70, 90, and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and
DQ6/DQ2 (toggle)
status bits.
After a program or
erase cycle has been completed, the device is ready to
read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29F200B
21526D4 November 1, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
4
4
5
6
6
7
8
DQ2: Toggle Bit II ................................................................... 18
Reading Toggle Bits DQ6/DQ2 ............................................... 18
DQ5: Exceeded Timing Limits ................................................ 19
DQ3: Sector Erase Timer ....................................................... 19
Figure 5. Toggle Bit Algorithm........................................................ 19
Table 6. Write Operation Status ..................................................... 20
Table 1. Am29F200B Device Bus Operations ..................................8
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode ................................................................ 9
Table 2. Am29F200T Top Boot Block Sector Address Table .........10
Table 3. Am29F200B Bottom Boot Block Sector Address Table ....10
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
TTL/NMOS Compatible .......................................................... 22
CMOS Compatible .................................................................. 23
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup....................................................................... 24
Table 7. Test Specifications ........................................................... 24
Key to Switching Waveforms. . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Operations .................................................................... 25
Figure 9. Read Operations Timings ............................................... 25
Autoselect Mode ..................................................................... 10
Table 4. Am29F200B Autoselect Codes (High Voltage Method) ....11
Hardware Reset (RESET#) .................................................... 26
Figure 10. RESET# Timings .......................................................... 26
Sector Protection/Unprotection ............................................... 11
Temporary Sector Unprotect .................................................. 11
Figure 1. Temporary Sector Unprotect Operation........................... 11
Word/Byte Configuration (BYTE#)
...................................... 27
Hardware Data Protection ...................................................... 11
Low V
CC
Write Inhibit ......................................................................12
Write Pulse “Glitch” Protection ........................................................12
Logical Inhibit ..................................................................................12
Power-Up Write Inhibit ....................................................................12
Figure 11. BYTE# Timings for Read Operations............................ 27
Figure 12. BYTE# Timings for Write Operations............................ 27
Erase/Program Operations ..................................................... 28
Figure 13. Program Operation Timings..........................................
Figure 14. Chip/Sector Erase Operation Timings ..........................
Figure 15. Data# Polling Timings (During Embedded Algorithms).
Figure 16. Toggle Bit Timings (During Embedded Algorithms)......
Figure 17. DQ2 vs. DQ6.................................................................
29
30
31
31
32
Command Definitions . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data ................................................................ 12
Reset Command ..................................................................... 12
Autoselect Command Sequence ............................................ 12
Word/Byte Program Command Sequence ............................. 13
Figure 2. Program Operation .......................................................... 13
Temporary Sector Unprotect .................................................. 32
Figure 18. Temporary Sector Unprotect Timing Diagram .............. 32
Alternate CE# Controlled Erase/Program Operations ............ 33
Figure 19. Alternate CE# Controlled Write Operation Timings ...... 34
Chip Erase Command Sequence ........................................... 13
Sector Erase Command Sequence ........................................ 14
Erase Suspend/Erase Resume Commands ........................... 14
Figure 3. Erase Operation............................................................... 15
Command Definitions ............................................................. 16
Table 5. Am29F200B Command Definitions ...................................16
DQ7: Data# Polling ................................................................. 17
Figure 4. Data# Polling Algorithm ................................................... 17
Erase and Programming Performance . . . . . . . . 35
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 35
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 35
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36
SO 044—44-Pin Small Outline Package ................................ 36
TS 048—48-Pin Standard Thin Small Outline Package ......... 37
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38
RY/BY#: Ready/Busy# ........................................................... 18
DQ6: Toggle Bit I .................................................................... 18
November 1, 2006 21526D4
Am29F200B
3
京公网安备 11010802033920号
EEWORLD
