Am29F010B KGD
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
23479
Revision
A
Amendment
0
Issue Date
October 23, 2003
SUPPLEMENT
Am29F010B Known Good Die
1 Megabit (128 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory—Die Revision 1
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 5.0 V ± 10% for read, erase, and program operations
— Simplifies system-level power requirements
■
Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■
High performance
— 90 or 120 ns maximum access time
■
Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■
Flexible sector architecture
— Eight uniform sectors
— Any combination of sectors can be erased
— Supports full chip erase
■
Sector protection
— Hardware-based feature that disables/re-enables
program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
■
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■
Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■
Minimum 1,000,000 program/erase cycles
guaranteed
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■
Data# Polling and Toggle Bits
— Provides a software method of detecting program
or erase cycle completion
■
Tested to datasheet specifications at
temperature
■
Quality and reliability levels equivalent to
standard packaged components
Publication#
23479
Rev:
A
Amendment/0
Issue Date:
October 23, 2003
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29F010B in Known Good Die (KGD) form is a
1 Mbit, 5.0 Volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same reli-
ability and quality as AMD products in packaged form.
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The de-
vice is designed to be programmed in-system with the
standard system 5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not
required for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
This device is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the
Embedded Pro-
gram
algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The
hardware data protection
measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of the sectors of memory, and is im-
plemented using standard EPROM programmers.
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
Electrical Specifications
Refer to the Am29F010B data sheet, publication
number 22336, for full electrical specifications for the
Am29F010B in KGD form.
2
Am29F010B Known Good Die
DSP and ARM Processors
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