Am29F010B
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
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Publication Number
Am29F010B_00
Revision
C
Amendment
7
Issue Date
October 31, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 5.0 V ± 10% for read, erase, and program operations
— Simplifies system-level power requirements
■
Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■
High performance
— 45 ns maximum access time
■
Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■
Flexible sector architecture
— Eight 16 Kbyte sectors
— Any combination of sectors can be erased
— Supports full chip erase
■
Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
■
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■
Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■
Minimum 1 million erase cycles guaranteed per
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■
Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication #
Am29F010B_00
Revision:
C
Amendment:
7
Issue Date:
October 31, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The de-
vice is designed to be programmed in-system with the
standard system 5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not
required for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
This device is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the
Embedded Pro-
gram
algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The
hardware data protection
measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of the sectors of memory, and is im-
plemented using standard EPROM programmers.
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
2
Am29F010B
Am29F010B_00_C7 October 31, 2006
D A T A
S H E E T
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 6
Standard Products .................................................................... 6
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Am29F010B Device Bus Operations .................................7
Reading Toggle Bit DQ6 ......................................................... 15
Figure 4. Toggle Bit Algorithm ........................................................ 15
DQ5: Exceeded Timing Limits ................................................ 15
DQ3: Sector Erase Timer ....................................................... 16
Table 5. Write Operation Status ..................................................... 16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 17
Figure 5. Maximum Negative Overshoot Waveform ...................... 17
Figure 6. Maximum Positive Overshoot Waveform ........................ 17
Requirements for Reading Array Data ..................................... 7
Writing Commands/Command Sequences .............................. 7
Program and Erase Operation Status ...................................... 8
Standby Mode .......................................................................... 8
Output Disable Mode ................................................................ 8
Table 2. Am29F010B Sector Addresses Table .................................8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 17
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Test Setup ....................................................................... 20
Table 6. Test Specifications ........................................................... 20
Key to Switching Waveforms . . . . . . . . . . . . . . . 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Read Operations Timings ............................................... 21
Autoselect Mode ....................................................................... 8
Table 3. Am29F010B Autoselect Codes (High Voltage Method) ......9
Erase and Program Operations .............................................. 22
Figure 9. Program Operation Timings ............................................ 23
Figure 10. Chip/Sector Erase Operation Timings .......................... 23
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 24
Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 24
Sector Protection/Unprotection ................................................. 9
Hardware Data Protection ........................................................ 9
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 10
Reading Array Data ................................................................ 10
Reset Command ..................................................................... 10
Autoselect Command Sequence ............................................ 10
Byte Program Command Sequence ....................................... 10
Figure 1. Program Operation ..........................................................11
Erase and Program Operations .............................................. 25
Figure 13. Alternate CE# Controlled Write Operation Timings ...... 26
Chip Erase Command Sequence ........................................... 11
Sector Erase Command Sequence ........................................ 11
Erase Suspend/Erase Resume Commands ........................... 12
Figure 2. Erase Operation ...............................................................12
Table 4. Am29F010B Command Definitions ...................................13
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 14
DQ7: Data# Polling ................................................................. 14
Figure 3. Data# Polling Algorithm ...................................................14
Erase and Programming Performance . . . . . . . 26
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 27
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 27
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 27
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 28
PD 032—32-Pin Plastic DIP ................................................... 28
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 29
TS 032—32-Pin Standard Thin Small Outline Package ......... 30
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 31
DQ6: Toggle Bit I .................................................................... 14
October 31, 2006 Am29F010B_00_C7
Am29F010B
3
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