Am29DS32xG
Data Sheet
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Publication Number
26493
Revision
A
Amendment
+0
Issue Date
May 15, 2002
ADVANCE INFORMATION
Am29DS32xG
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
■
Multiple bank architectures
— Three devices available with different bank sizes
(refer to Table 3)
■
256-byte SecSi (Secured Silicon) Sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
One time programmable. Once
locked, data cannot be changed.
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■
Package options
— 48-ball FBGA
— 48-pin TSOP
■
Top or bottom boot block
■
Manufactured on 0.17 µm process technology
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast 60 ns
— Program time: 4 µs/word typical utilizing Accelerate
function
■
Ultra low power consumption (typical values)
— 1 mA active read current at 1 MHz
— 5 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million write cycles guaranteed per sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
26493
Rev:
A
Issue Date:
May 15, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29DS32xG family consists of 32 megabit, 1.8
volt-only flas h memory dev ices, or ganiz ed as
2,097,152 words of 16 bits each or 4,194,304 bytes of
8 bits each. Word mode data appears on DQ15–DQ0;
byte mode data appears on DQ7–DQ0. The device is
designed to be programmed in-system with the stan-
dard 1.8 volt V
CC
supply, and can also be programmed
in standard EPROM programmers.
The devices are available with an access time of 60,
70, 90, or 120 ns. (An 80 ns speed option at the stan-
dard voltage range is also available. Contact AMD or
an AMD representative for more information.) The de-
vices are offered in 48-pin TSOP and 48-ball FBGA
packages. Standard control pins—chip enable (CE#),
write enable (WE#), and output enable (OE#)—control
normal read and write operations, and avoid bus con-
tention issues.
The devices requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a dv a n ta ge c om pa r e d to s y s te ms wh e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DS32xG device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
Device
DS322
DS323
DS324
Bank 1
4
8
16
Bank 2
28
24
16
Am29DS32xG Features
The
SecSi
TM
(Secured Silicon) Sector
is an extra sector
capable of being permanently locked by AMD or cus-
tomers. The
SecSi Indicator Bit
(DQ7) is perma-
nently set to a 1 if the part is
factory locked,
and set
to a 0 if
customer lockable.
This way, customer lock-
able parts can never be used to replace a factory
locked part.
Current version of device has 256
bytes, which differs from previous versions of this
device.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
2
Am29DS32xG
May 15, 2002
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .......................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations ...........................................................10
Unlock Bypass Command Sequence ........................................... 27
Figure 3. Program Operation ................................................................ 27
Chip Erase Command Sequence ................................................. 27
Sector Erase Command Sequence .............................................. 28
Erase Suspend/Erase Resume Commands ................................ 28
Figure 4. Erase Operation .................................................................... 29
Table 14. Command Definitions ........................................................... 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ...................................................................... 31
Figure 5. Data# Polling Algorithm ......................................................... 31
Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data ......................................... 10
Writing Commands/Command Sequences .................................. 11
Accelerated Program Operation ...................................................11
Autoselect Functions .................................................................... 11
Simultaneous Read/Write Operations
with Zero Latency ......................................................................... 11
Standby Mode .............................................................................. 11
Automatic Sleep Mode ................................................................. 11
RESET#: Hardware Reset Pin .....................................................12
Output Disable Mode ................................................................... 12
Table 2. Device Bank Divisions .............................................................12
Table 3. Top Boot Sector Addresses ...................................................13
Table 4. Top Boot SecSi
TM
Sector Addresses ..................................... 14
Table 5. Bottom Boot Sector Addresses ...............................................16
Table 6. Bottom Boot SecSi
TM
Sector Addresses ................................ 17
RY/BY#: Ready/Busy# ................................................................. 32
DQ6: Toggle Bit I .......................................................................... 32
Figure 6. Toggle Bit Algorithm .............................................................. 32
DQ2: Toggle Bit II ......................................................................... 33
Reading Toggle Bits DQ6/DQ2 .................................................... 33
DQ5: Exceeded Timing Limits ...................................................... 33
DQ3: Sector Erase Timer ............................................................. 33
Table 15. Write Operation Status ......................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ............................. 35
Figure 8. Maximum Positive Overshoot Waveform .............................. 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents).................................................................... 37
Figure 10. Typical I
CC1
vs. Frequency................................................... 37
Autoselect Mode .......................................................................... 18
Table 7. Autoselect Codes, (High Voltage Method) .............................18
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup .......................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ........................ 38
Sector/Sector Block Protection and Unprotection ........................ 19
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................19
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Read Operation Timings...................................................... 39
Figure 14. Reset Timings...................................................................... 40
Word/Byte Configuration (BYTE#) ............................................... 41
Figure 15. BYTE# Timings for Read Operations .................................. 41
Figure 16. BYTE# Timings for Write Operations .................................. 41
Write Protect (WP#) ..................................................................... 20
Temporary Sector Unprotect ........................................................ 20
Figure 1. Temporary Sector Unprotect Operation................................. 20
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 21
Erase and Program Operations ................................................... 42
Figure 17. Program Operation Timings ................................................
Figure 18. Accelerated Program Timing Diagram ................................
Figure 19. Chip/Sector Erase Operation Timings .................................
Figure 20. Back-to-back Read/Write Cycle Timings .............................
Figure 21. Data# Polling Timings (During Embedded Algorithms) .......
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............
Figure 23. DQ2 vs. DQ6 .......................................................................
43
43
44
45
45
46
46
SecSi
TM
(Secured Silicon) Sector
Flash Memory Region .................................................................. 22
Factory Locked: SecSi Sector Programmed and Protected At the
Factory ......................................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Protected At
the Factory ...................................................................................22
Hardware Data Protection ............................................................ 22
Low VCC Write Inhibit .................................................................. 23
Write Pulse “Glitch” Protection .....................................................23
Logical Inhibit ...............................................................................23
Power-Up Write Inhibit ................................................................. 23
Temporary Sector Unprotect ........................................................ 47
Figure 24. Temporary Sector Unprotect Timing Diagram ..................... 47
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 48
Alternate CE# Controlled Erase and Program Operations ........... 49
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 50
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 10. CFI Query Identification String ..............................................
Table 11. System Interface String.........................................................
Table 12. Device Geometry Definition ..................................................
Table 13. Primary Vendor-Specific Extended Query ............................
23
24
24
25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 26
Autoselect Command Sequence ..................................................26
Enter SecSi
TM
Sector/Exit SecSi Sector
Command Sequence ................................................................... 26
Byte/Word Program Command Sequence ................................... 26
Erase And Programming Performance . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 51
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
..................................................................................................... 51
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 52
TS 048—Thin Small Outline Package .......................................... 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision A (May 15, 2002) ........................................................... 54
May 15, 2002
Am29DS32xG
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Speed Rating
Standard Voltage Range: V
CC
= 1.8–2.2 V
70
70
70
30
Am29DS32xG
90
90
90
40
120
120
120
120
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
BLOCK DIAGRAM
OE# BYTE#
V
CC
V
SS
Y-Decoder
A20–A0
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ15–DQ0
A20–A0
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
DQ15–DQ0
Control
DQ15–DQ0
X-Decoder
Lower Bank
A20–A0
Lower Bank Address
OE# BYTE#
4
Am29DS32xG
Latches and
Control Logic
Y-Decoder
DQ15–DQ0
A20–A0
May 15, 2002
DSP and ARM Processors
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