Am29DL800B
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21519
Revision
C
Amendment
4
Issue Date
December 4, 2006
Publication Number
21519
Revision
C
Amendment
4
Issue Date
December 4, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29DL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Simultaneous Read/Write operations
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Zero latency between read and write operations
— Read-while-erase
— Read-while-program
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
■
Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29DL800 device
■
High performance
— Access times as fast as 70 ns
■
Low current consumption (typical values
at 5 MHz)
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 17 mA active program-while-erase-suspended current
— 200 nA in standby mode
— 200 nA in automatic sleep mode
— Standard t
CE
chip enable access time applies to
transition from automatic sleep mode to active mode
■
Flexible sector architecture
— Two 16 Kword, two 8 Kword, four 4 Kword, and
fourteen 32 Kword sectors in word mode
— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
fourteen 64 Kbyte sectors in byte mode
— Any combination of sectors can be erased
— Supports full chip erase
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Sector protection
— Hardware method of locking a sector to prevent
any program or erase operation within that sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top or bottom boot block configurations
available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
— Embedded Program algorithm automatically
programs and verifies data at specified address
■
Minimum 1,000,000 program/erase cycles
guaranteed per sector
■
Package options
— 44-pin SO
— 48-pin TSOP
— 48-ball FBGA
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Superior inadvertent write protection
■
Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— No need to suspend if sector is in the other bank
■
Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
Publication#
21519
Rev:
C
Amendment:
4
Issue Date:
December 4, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29DL800B is an 8 Mbit, 3.0 volt-only flash
memory device, organized as 524,288 words or
1,048,576 bytes. The device is offered in 44-pin SO,
48-pin TSOP, and 48-ball FBGA packages. The word-
wide (x16) data appears on DQ0–DQ15; the byte-wide
(x8) data appears on DQ0–DQ7. This device requires
only a single 3.0 volt V
CC
supply to perform read, pro-
gram, and erase operations. A standard EPROM
programmer can also be used to program and erase
the device.
This device is manufactured using AMD’s 0.35 µm pro-
cess technology, and offers all the features and
benefits of the Am29DL800, which was manufactured
using a 0.5 µm technology.
The standard device offers access times of 70, 90, and
120 ns, allowing high-speed microprocessors to oper-
ate without wait states. Standard control pins—chip
enable (CE#), write enable (WE#), and output enable
(OE#)—control read and write operations, and avoid
bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device automatically returns to
reading array data.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The
hardware sector protec-
tion
feature disables both program and erase operations
in any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enabling the sys-
tem microprocessor to read the boot-up firmware from
the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte or word
at a time using hot electron injection.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
si-
multaneous operation
by dividing the memory space
into two banks. Bank 1 contains eight boot/parameter
sectors, and Bank 2 consists of fourteen larger, code
sectors of uniform size. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with
zero la-
tency.
This releases the system from waiting for the
completion of program or erase operations.
Am29DL800B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command reg-
ister using standard microprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase opera-
tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
2
Am29DL800B
21519C4 December 4, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DL800B Device Bus Operations ................................9
Reading Toggle Bits DQ6/DQ2 ............................................... 22
Figure 6. Toggle Bit Algorithm........................................................ 23
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Table 6. Write Operation Status ......................................................24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 7. Maximum Negative Overshoot Waveform ..................... 25
Figure 8. Maximum Positive Overshoot Waveform....................... 25
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29DL800BT Top Boot Sector Architecture ..................12
Table 3. Am29DL800BB Bottom Boot Sector Architecture .............13
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 10. Typical I
CC1
vs. Frequency ........................................... 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Test Setup.................................................................... 28
Table 7. Test Specifications ........................................................... 28
Key to Switching Waveforms . . . . . . . . . . . . . . . 28
Figure 12. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Read Operation Timings ...............................................
Figure 14. Reset Timings ...............................................................
Figure 15. BYTE# Timings for Read Operations............................
Figure 16. BYTE# Timings for Write Operations............................
Figure 17. Program Operation Timings..........................................
Figure 18. Chip/Sector Erase Operation Timings ..........................
Figure 19. Back-to-Back Read/Write Cycle Timings ......................
Figure 20. Data# Polling Timings (During Embedded Algorithms).
Figure 21. Toggle Bit Timings (During Embedded Algorithms)......
Figure 22. DQ2 vs. DQ6.................................................................
Figure 23. Temporary Sector Unprotect Timing Diagram ..............
Figure 24. Sector Protect/Unprotect Timing Diagram ....................
29
30
31
31
33
33
34
34
35
35
36
36
Autoselect Mode ..................................................................... 13
Table 4. Am29DL800B Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 14
Figure 1. Temporary Sector Unprotect Operation........................... 14
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 15
Erase and Program Operations .............................................. 32
Hardware Data Protection ...................................................... 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Byte/Word Program Command Sequence ............................. 17
Figure 3. Program Operation .......................................................... 18
Alternate CE# Controlled Erase/Program Operations ............ 37
Figure 25. Alternate CE# Controlled Erase/Program
Operation Timings.......................................................................... 38
Chip Erase Command Sequence ........................................... 18
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 19
Figure 4. Erase Operation............................................................... 19
Command Definitions ............................................................. 20
Table 5. Am29DL800B Command Definitions ................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 5. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Erase and Programming Performance . . . . . . . 39
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................ 40
FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA),
6 x 9 mm package .................................................................. 41
SO 044—44-Pin Small Outline .............................................. 42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
December 4, 2006 21519C4
Am29DL800B
3
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