3D7215
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7215 – LOW NOISE)
FEATURES
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All-silicon, low-power 5V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
1ns through 250ns
Delay tolerance:
2% or 1ns
Temperature stability:
±1%
typical (0C-70C)
Vdd stability:
±0.5%
typical (3.0V-3.6V)
Static Idd:
1.5ma typical
Minimum input pulse width:
20% of total delay
IN
O2
O4
GND
1
2
3
4
8
7
6
5
PACKAGES
VDD
O1
O3
O5
IN
O2
O4
GND
1
2
3
4
8
7
6
5
VDD
O1
O3
O5
3D7215Z-xx
SOIC
(150 Mil)
3D7215M-xx DIP (300 Mil)
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
The 3D7215 5-Tap Delay Line product family consists of fixed-delay 5V
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 1ns through 50ns. The input
is reproduced at the outputs without inversion, shifted in time as per the
user-specified dash number. The 3D7215 is 5V CMOS-compatible and
features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VDD
GND
N/C
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+5 Volts
Ground
No Connection
The all-CMOS 3D7215 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in
a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D7215Z-xx
3D7215M-xx
-1
-1.5
-2
-2.5
-3
-4
-5
-6
-8
-10
-12
-15
-20
-25
-30
-40
-50
DELAY SPECIFICATIONS
TOTAL
TAP-TAP
DELAY (ns)
DELAY (ns)
4.0
±
1.0*
1.0
±
0.5
6.0
±
1.0*
1.5
±
0.7
8.0
±
1.0*
2.0
±
0.8
10.0
±
1.0*
2.5
±
1.0
12.0
±
1.0*
3.0
±
1.3
16.0
±
1.0*
4.0
±
1.3
20.0
±
1.0*
5.0
±
1.4
24.0
±
1.0*
6.0
±
1.4
40.0
±
1.0
8.0
±
1.4
50.0
±
1.0
10.0
±
1.5
60.0
±
1.2
12.0
±
1.5
75.0
±
1.5
15.0
±
1.5
100
±
2.0
20.0
±
2.0
125
±
2.5
25.0
±
2.5
150
±
3.0
30.0
±
3.0
200
±
4.0
40.0
±
4.0
250
±
5.0
50.0
±
5.0
INPUT RESTRICTIONS
RECOMMENDED
ABSOLUTE
Max Freq
Min P.W.
Max Freq
Min P.W.
27.8 MHz
18.0 ns
166.7 MHz
3.00 ns
23.8 MHz
21.0 ns
153.8 MHz
3.25 ns
20.8 MHz
24.0 ns
142.8 MHz
3.50 ns
18.5 MHz
27.0 ns
133.3 MHz
3.75 ns
16.7 MHz
30.0 ns
125.0 MHz
4.00 ns
13.9 MHz
36.0 ns
111.1 MHz
4.50 ns
11.9 MHz
42.0 ns
100.0 MHz
5.00 ns
10.4 MHz
48.0 ns
83.3 MHz
6.00 ns
8.33 MHz
60.0 ns
62.5 MHz
8.00 ns
6.67 MHz
75.0 ns
50.0 MHz
10.00 ns
5.56 MHz
90.0 ns
41.7 MHz
12.00 ns
4.42 MHz
113 ns
33.3 MHz
15.00 ns
3.33 MHz
150 ns
25.0 MHz
20.00 ns
2.66 MHz
188 ns
20.0 MHz
25.00 ns
2.22 MHz
225 ns
16.7 MHz
30.00 ns
1.67 MHz
300 ns
12.5 MHz
40.00 ns
1.33 MHz
375 ns
10.0 MHz
50.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns
±
1.5ns
NOTE: Any dash number between 1 and 50 not shown is also available as standard product
2002
Data Delay Devices
Doc #01015
11/8/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7215
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7215 five-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
the delay line input signal for which the output
delay accuracy is guaranteed. To guarantee the
Table 1
delay accuracy for input frequencies
higher than the
Recommended Maximum
Frequency,
the 3D7215 must be tested at the
user operating frequency. Therefore, to facilitate
production and device identification,
the part
number will include a custom reference
designator
identifying the intended frequency of
operation. The programmed delay accuracy of
the device is guaranteed, therefore, only at the
user specified input frequency. Small input
frequency variation about the selected frequency
will only marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a
Recommended Maximum
and an
Absolute
Maximum
operating input frequency and a
Recommended Minimum
and an
Absolute
Minimum
operating pulse width have been
specified.
OPERATING PULSE WIDTH
The
Absolute Minimum Pulse Width
(high or
low) specification, tabulated in
Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion.
The
Recommended Minimum Pulse Width
(high or low) specification determines the
smallest Pulse Width of the delay line input signal
for which the output delay accuracy tabulated in
Table 1
is guaranteed.
To guarantee the
Table 1
delay accuracy for
input pulse width smaller than the
Recommended Minimum Pulse Width,
the
3D7215 must be tested at the user operating
IN
O1
O2
O3
O4
O5
OPERATING FREQUENCY
The
Absolute Maximum Frequency
specification, tabulated in
Table 1,
determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The
Recommended Maximum Frequency
specification determines the highest frequency of
IN O1
O2
O3
O4
O5
25%
25%
25%
25%
20%
20%
20%
20%
20%
Temp & VDD
Compensation
Temp & VDD
Compensation
VDD
Dash numbers < 8
GND
VDD
Dash numbers >= 8
GND
Figure 1: 3D7215 Functional Diagram
Doc #01015
11/8/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7215
APPLICATION NOTES (CONT’D)
pulse width. Therefore, to facilitate production
and device identification, the
part number will
include a custom reference designator
identifying the intended frequency and duty cycle
of operation. The programmed delay accuracy of
the device is guaranteed, therefore, only for the
user specified input characteristics. Small input
pulse width variation about the selected pulse
width will only marginally impact the programmed
delay accuracy, if at all.
Nevertheless, it is
strongly recommended that the engineering
staff at DATA DELAY DEVICES be consulted.
and innovative compensation circuitry to
minimize the delay variations induced by
fluctuations in power supply and/or temperature.
The
thermal coefficient
is reduced to
200
PPM/C,
which is equivalent to a variation , over
the 0C-70C operating range, of
±1%
from the
room-temperature delay settings and/or
1.0ns,
whichever is greater. The
power supply
coefficient
is reduced, over the 4.75V-5.25V
operating range, to
±0.5%
of the delay settings at
the nominal 5.0VDC power supply and/or
0.5ns,
whichever is greater.
It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7215 delay line utilizes novel
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
Input Threshold Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
TH
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.2
MAX
1.5
2.8
1
1
-4.0
UNITS
mA
V
µA
µA
mA
mA
2
ns
NOTES
4.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 5.0V
V
OH
= 4.0V
V
DD
= 5.0V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 5 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #01015
11/8/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7215
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 5.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 1.0V and 4.0V )
Pulse Width:
PW
IN
= 1.5 x Total Delay
Period:
PER
IN
= 3.0 x Total Delay
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
2.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT1
OUT2
OUT3
OUT4
OUT5
REF
IN
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
PER
IN
PW
IN
t
RISE
INPUT
SIGNAL
4.0
2.5
1.0
t
FALL
V
IH
4.0
2.5
1.0
V
IL
t
PHL
t
PLH
OUTPUT
SIGNAL
2.5
V
OH
2.5
V
OL
Figure 3: Timing Diagram
Doc #01015
11/8/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
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