3D7225Z-.75 datasheet, PDF - EEWORLD Datasheet

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3D7225Z-.75: DescriptionMONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225); Categorylogic logic; File Size125KB，4 Pages; ManufacturerData Delay Devices

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MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225)

3D7225Z-.75 Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	compli
Base Number Matches	1

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3D7225

MONOLITHIC 5-TAP

FIXED DELAY LINE

(SERIES 3D7225)

FEATURES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range:

0.75ns through 3500ns

Delay tolerance:

2% or 0.5ns

Temperature stability:

±2%

typical (-40C to 85C)

Vdd stability:

±1%

typical (4.75V-5.25V)

Minimum input pulse width:

30% of total delay

8-pin Gull-Wing available as drop-in

replacement for hybrid delay lines

GND

PACKAGES

VDD

GND

VDD

3D7225Z-xx SOIC-8

3D7225M-xx DIP-8

3D7225H-xx Gull-Wing

GND

VDD

3D7225-xx

3D7225G-xx

3D7225K-xx

3D7225S-xx SOL-16

DIP-14

Gull-Wing

Unused pins

removed

For mechanical dimensions, click

here

For package marking details, click

here

FUNCTIONAL DESCRIPTION

The 3D7225 5-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 700ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D7225 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

PIN DESCRIPTIONS

VDD

GND

Delay Line Input

Tap 1 Output (20%)

Tap 2 Output (40%)

Tap 3 Output (60%)

Tap 4 Output (80%)

Tap 5 Output (100%)

+5 Volts

Ground

The all-CMOS 3D7225 integrated circuit has been designed as a reliable, economic alternative to hybrid

TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and space saving surface mount

8-pin SOIC and 16-pin SOL packages.

TABLE 1: PART NUMBER SPECIFICATIONS

DASH

NUMBER

-.75

-1

-1.5

-2

-2.5

-4

-5

-10

-20

-50

-100

-200

-700

TOLERANCES

TOTAL

TAP-TAP

DELAY (ns)

3.0

0.5*

0.75

0.4

4.0

0.5*

1.0

0.5

6.0

0.5*

1.5

0.7

8.0

0.5*

2.0

0.8

10.0

0.5*

2.5

1.0

16.0

0.7*

4.0

1.3

25.0

1.0

5.0

1.5

50.0

1.0

10.0

2.0

100.0

2.0

20.0

4.0

250.0

5.0

50.0

500.0

100

1000

200

3500

700

140

Rec’d Max

Frequency

41.7 MHz

37.0 MHz

31.2 MHz

25.0 MHz

22.2 MHz

8.33 MHz

13.3 MHz

6.67 MHz

3.33 MHz

1.33 MHz

0.67 MHz

0.33 MHz

0.10 MHz

INPUT RESTRICTIONS

Absolute Max

Rec’d Min

Frequency

Pulse Width

166.7 MHz

12.0 ns

166.7 MHz

13.5 ns

166.7 MHz

16.0 ns

166.7 MHz

20.0 ns

125.0 MHz

22.5 ns

133.3 MHz

30.0 ns

66.7 MHz

37.5 ns

33.3 MHz

75.0 ns

16.7 MHz

150 ns

6.67 MHz

375 ns

3.33 MHz

750 ns

1.67 MHz

1500 ns

0.48 MHz

5250 ns

Absolute Min

Pulse Width

3.00 ns

4.00 ns

6.00 ns

7.50 ns

15.0 ns

30.0 ns

75.0 ns

150 ns

300 ns

1050 ns

2005

Data Delay Devices

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns

1.0ns

NOTE: Any dash number between .75 and 700 not shown is also available as standard.

Doc #05002

4/15/05

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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