SUPPLEMENT
Am29BL162C Known Good Die
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only, Burst-Mode, Boot Sector Flash Memory—Die
Revision 1
DISTINCTIVE CHARACTERISTICS
■
32 words sequential with wrap around (linear
32), bottom boot
■
One 8 Kword, two 4 Kword, one 112 Kword, and
seven 128 Kword sectors
■
Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
Read access times
22 ns burst access
(at extended temperature range)
80 ns initial/random access
■
Alterable burst length via BAA# pin
■
Power dissipation (typical)
— Burst Mode Read: 15 mA @ 25 MHz,
20 mA @ 33 MHz
— Program/Erase: 20 mA
— Standby mode, CMOS: 22 µA
■
5 V-tolerant data, address, and control signals
■
Sector Protection
— Implemented using in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 100,000 erase cycle guarantee
per sector
■
20-year data retention at 125°C
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— Backward-compatible with AMD Am29LV and
Am29F flash memories: powers up in
asynchronous mode for system boot, but can
immediately be placed into burst mode
■
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■
Tested to datasheet specifications at
temperature
■
Quality and reliability levels equivalent to
standard packaged components
Publication#
23783
Rev:
A
Amendment/+4
Issue Date:
April 29, 2003
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29BL162C in Known Good Die (KGD) form is a
16 Mbit, 3.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same reliability
and quality as AMD products in packaged form.
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations dur-
ing power transitions. The
hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Am29BL162C Features
The Am29BL162C is organized as 1,048,576 words. It
is designed to be programmed in-system with the stan-
dard system 3.0-volt V
CC
supply. A 12.0-volt V
PP
or 5.0
V
CC
is not required for program or erase operations.
The device can also be programmed in standard
EPROM programmers.
The device offers access times of 80 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
Burst Mode Features
The Am29BL162C offers a Linear Burst mode—a
32 word sequential burst with wrap around—in a
bottom boot configuration only. This devices require
additional control pins for
burst operations:
Load
Burst Address (LBA#), Burst Address Advance
(BAA#), and Clock (CLK). This implementation allows
easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high perfor-
mance read operations.
AMD Flash Memory Features
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. The I/O and control
signals are 5V tolerant.
The Am29BL162C is entirely command set compatible
with the
JEDEC single-power-supply Flash stan-
dard.
Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
Electrical Specifications
Refer to the Am29BL162C data sheet, publication
number 22142, for full electrical specifications on the
Am29BL162C in KGD form.
2
Am29BL162C Known Good Die
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