3D7418
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7418 – LOW NOISE)
FEATURES
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All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Increment range:
0.25 through 5.0ns
Delay tolerance:
1% (See Table 1)
Temperature stability:
±3%
typical (0C-70C)
Vdd stability:
±1%
typical (4.75V-5.25V)
Minimum input pulse width:
10% of total
delay
Programmable via 3-wire serial or 8-bit
parallel interface
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PACKAGES
VDD
OUT
MD
P7
P6
SC
P5
SI
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7418 DIP
3D7418G Gull Wing
3D7418S SOL
(300 Mil)
For mechanical dimensions, click
here
.
FUNCTIONAL DESCRIPTION
The 3D7418 Programmable 8-Bit Silicon Delay Line product family
consists of 8-bit, user-programmable CMOS silicon integrated
circuits. Delay values, programmed either via the serial or parallel
interface, can be varied over 255 equal steps ranging from 250ps
to 5.0ns inclusively. Units have a typical inherent (zero step)
delay of 12ns to 17ns (See Table 1). The input is reproduced at
the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten
74LS-type loads, and features both rising- and falling-edge
accuracy.
PIN DESCRIPTIONS
IN
OUT
MD
AE
P0-P7
SC
SI
SO
VDD
GND
Signal Input
Signal Output
Mode Select
Address Enable
Parallel Data Input
Serial Clock
Serial Data Input
Serial Data Output
+5 Volts
Ground
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7418-0.25
3D7418-0.5
3D7418-1
3D7418-2
3D7418-3
3D7418-4
3D7418-5
DELAYS AND TOLERANCES
Step 0
Delay (ns)
12
±
2
12
±
2
12
±
2
14
±
2
17
±
2
17
±
2
17
±
2
Step 255
Delay (ns)
75.75
±
4.0
139.5
±
4.0
267.0
±
5.0
522.0
±
6.0
782.0
±
8.0
1037
±
9.0
1292
±
10
Delay
Increment (ns)
0.25
±
0.15
0.50
±
0.25
1.00
±
0.50
2.00
±
1.00
3.00
±
1.50
4.00
±
2.00
5.00
±
2.50
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
INPUT RESTRICTIONS
Absolute Max
Oper Freq
90 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
Min Operating
P.W.
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
Absolute Min
Oper P.W.
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
2002
Data Delay Devices
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7418
APPLICATION NOTES
The 8-bit programmable 3D7418 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (OUT)
by the user-selected programming data. Each
delay cell produces at its output a replica of the
signal present at its input, shifted in time.
OPERATING PULSE WIDTH
The
Absolute Minimum Operating Pulse
Width
(high or low) specification, tabulated in
Table 1,
determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The
Minimum Operating Pulse Width
(high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in
Table 1
is
guaranteed.
To guarantee the
Table 1
delay accuracy for
input pulse width smaller than the
Minimum
Operating Pulse Width,
the 3D7418 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the
part number will include a
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay and increment accuracy of the particular
device. The reasons for the dependency of the
output delay accuracy on the input signal
characteristics are varied and complex.
Therefore a
Maximum
and an
Absolute
Maximum
operating input frequency and a
Minimum
and an
Absolute Minimum
operating
pulse width have been specified.
OPERATING FREQUENCY
The
Absolute Maximum Operating Frequency
specification, tabulated in
Table 1,
determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The
Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the
Table 1
delay accuracy for
input frequencies higher than the
Maximum
Operating Frequency,
the 3D7418 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification,
the part number will include a
custom reference designator
identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
SPECIAL HIGH ACCURACY
REQUIREMENTS
The
Table 1
delay and increment accuracy
specifications are aimed at meeting the
requirements of the majority of the applications
encountered to date. However, some systems
may place tighter restrictions on one accuracy
parameter in favor of others. For example, a
channel delay equalizing system is concerned in
minimizing delay variations among the various
channels. Therefore, because the inter channel
skew is a delay difference, the programmed
delay tolerance may need to be considerably
decreased, while the increment and its tolerance
are of no consequence. The opposite is true for
an under-sampled multi-channel data acquisition
system.
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7418
APPLICATION NOTES (CONT’D)
The flexible 3D7418 architecture can be
exploited to conform to these more demanding
user-dictated accuracy constraints. However, to
facilitate production and device identification,
the
part number will include a custom reference
designator
identifying the user requested
accuracy specifications and operating conditions.
It is strongly recommended that the
engineering staff at DATA DELAY DEVICES
be consulted.
In order to ensure that spurious outputs do not
occur, it is essential that the input signal be idle
(held high or low) for a short duration prior to
updating the programmed delay. This duration is
given by the maximum programmable delay.
Satisfying this requirement allows the delay line
to “clear” itself of spurious edges. When the new
address is loaded, the input signal can begin to
switch (and the new delay will be valid) after a
time given by
t
PDV
or
t
EDV
(see section below).
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7418 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
600
PPM/C,
which is equivalent to a variation, over
the 0C-70 C operating range, of
±3%
from the
room-temperature delay settings. The
power
supply coefficient
is reduced, over the 4.75V-
5.25V operating range, to
±1%
of the delay
settings at the nominal 5.0VDC power supply
and/or
±2ns,
whichever is greater.
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
PROGRAMMED DELAY (ADDRESS)
INTERFACE
Figure 1
illustrates the main functional blocks of
the 3D7418 delay program interface. Since the
3D7418 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VCC or Ground.
TRANSPARENT PARALLEL MODE
(MD = 1, AE = 1)
The eight program pins P0 - P7 directly control
the output delay. A change on one or more of
the program
pins will be reflected on the output delay after a
time
t
PDV
, as shown in
Figure 2.
A register is
required if the programming data is bused.
LATCHED PARALLEL MODE
(MD = 1, AE PULSED)
The eight program pins P0 - P7 are loaded by the
falling edge of the Enable pulse, as shown in
Figure 3.
After each change in delay value, a
settling time
t
EDV
is required before the input is
accurately delayed.
PROGRAMMED DELAY (ADDRESS)
UPDATE
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output with minimal distortion. The 3D7418 8-bit
programmable delay line can be represented by
256 serially connected delay elements
(individually
addressed
by the programming
data), each capable of storing data for a time
equal to the device increment (step time). The
delay line memory property, in conjunction with
the operational requirement of “instantaneously”
connecting the delay element addressed by the
programming data to the output, may inject
spurious information onto the output data stream.
SERIAL MODE (MD = 0)
While observing data setup (t
DSC
) and data hold
(t
DHC
) requirements, timing data is loaded in
MSB-to-LSB order by the rising edge of the clock
(SC) while the enable (AE) is high, as shown in
Figure 4.
The falling edge of the enable (AE)
activates the new delay value which is reflected
at the output after a settling time
t
EDV
. As data is
shifted into the serial data input (SI), the previous
contents of the 8-bit input register are shifted out
of the serial output port pin (SO) in MSB-to-LSB
order, thus allowing cascading of multiple
devices by connecting the serial output pin (SO)
of the preceding device to the serial data input
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7418
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5.
The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time
t
EQV
, bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
SIGNAL IN
IN
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
Pin 3, if unused,
must be allowed to float
if the
device is configured in the serial programming
mode.
PROGRAMMABLE
DELAY LINE
OUT SIGNAL OUT
ADDRESS ENABLE
AE
LATCH
8-BIT INPUT
REGISTER
SO
SERIAL OUTPUT
SERIAL INPUT SI
SHIFT CLOCK
MODE SELECT
SC
MD
P0
P1
P2
P3
P4
P5
P6
P7
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS VALUE
NEW VALUE
t
PDX
PREVIOUS VALUE
t
PDV
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
t
EW
ENABLE
(AE)
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS VALUE
t
DSE
NEW VALUE
t
DHE
t
EDV
NEW VALUE
t
EDX
Figure 3: Latched parallel mode (MD=1)
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
3D7418
APPLICATION NOTES (CONT’D)
t
EW
ENABLE
(AE)
t
ES
CLOCK
(SC)
SERIAL
INPUT
(SI)
SERIAL
OUTPUT
(SO)
DELAY
TIME
t
CW
t
CW
t
EH
t
DSC
NEW
BIT 7
t
DHC
NEW
BIT 6
NEW
BIT 0
t
EGV
OLD
BIT 7
t
CQV
OLD
BIT 6
t
CQX
OLD
BIT 0
t
EQZ
t
EDV
NEW
VALUE
t
EDX
PREVIOUS VALUE
Figure 4: Serial mode (MD=0)
SI
3D7418
AE
SO
SI
3D7418
SC
AE
SO
SI
3D7418
SC
AE
SO
FROM
WRITING
DEVICE
SC
TO
NEXT
DEVICE
Figure 5: Cascading Multiple Devices
TABLE 2: DELAY VS. PROGRAMMED ADDRESS
PARALLEL
SERIAL
STEP 0
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 253
STEP 254
STEP 255
DELAY CHANGE
PROGRAMMED ADDRESS
P7
P6
P5
P4
Msb
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
P3
0
0
0
0
0
0
1
1
1
P2
0
0
0
0
1
1
1
1
1
P1
0
0
1
1
0
0
0
1
1
P0
Lsb
0
1
0
1
0
1
1
0
1
NOMINAL DELAY (NS)
3D7418 DASH NUMBER
-.25
-.5
-1
12.00
12.0
12
12.25
12.5
13
12.50
13.0
14
12.75
13.5
15
13.00
14.0
16
13.25
14.5
17
75.25
75.50
75.75
63.75
138.5
139.0
139.5
127.5
265
266
267
255
-2
12
14
16
18
20
22
-5
17
22
27
32
37
42
1283
1287
1292
1275
518
520
522
510
Doc #02005
6/17/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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