Am29BDS128H/Am29BDS640H
Data Sheet
(
RETIRED
PRODUCT
(AM29BDS40H ONLY)
The Am29BDS640H has been retired and is not recommended for designs. For new designs,
S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for speci-
fications and ordering information. The Am29BDS128H is available and is not affected by this revi-
sion.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary. Future routine revisions will occur when appropriate, and changes will
be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support the Am29BDS640H part numbers. To order these products, please
use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
27024
Revision
B
Amendment
3
Issue Date
May 10, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BDS128H/Am29BDS640H
128 or 64 Megabit (8 M or 4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for
specifications and ordering information. The Am29BDS128H is available and is not affected by this revision.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
■
■
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
Manufactured on 0.13 µm process technology
VersatileIO™ (V
IO
) Feature
— Device generates data output voltages and tolerates data
input voltages as determined by the voltage on the V
IO
pin
— 1.8V compatible I/O signals
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture:
128 Mb has 16/48/48/16 Mbit banks
64 Mb has 8/24/24/8 Mbit banks
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Sector Architecture
— Banks A and D each contain both 4 Kword sectors and 32
Kword sectors; Banks B and C contain ninety-six 32 Kword
sectors
— Sixteen 4 Kword boot sectors
Half of the boot sectors are at the top of the address range;
half are at the bottom of address range
Minimum 1 million erase cycle guarantee per sector
20-year data retention at 125°C
— Reliable operation for the life of the system
80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb)
package
■
HARDWARE FEATURES
■
Handshaking feature
— Provides host system with minimum possible latency by
monitoring RDY
— Reduced Wait-state handshaking option further reduces
initial access cycles required for burst accesses beginning on
even addresses
■
■
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array data
WP# input
— Write protect (WP#) function allows protection of the four
highest and four lowest 4 kWord boot sectors, regardless of
sector protect status
Persistent Sector Protection
— A command sector protection method to lock combinations of
individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
■
■
■
■
■
■
■
■
SOFTWARE FEATURES
■
■
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
— Backwards compatible with Am29F and Am29LV families
Data# Polling and toggle bits
— Provides a software method of detecting program and erase
operation completion
Erase Suspend/Resume
— Suspends an erase operation to read data from, or program
data to, a sector that is not being erased, then resumes the
erase operation
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
Burst Suspend/Resume
— Suspends a burst operation to allow system use of the
address and data bus, than resumes the burst at the previous
state
Publication#
27024
Rev:
B
Amendment:
3
Issue Date:
May 10, 2006
■
■
■
■
PERFORMANCE CHARCTERISTICS
■
Read access times at 75/66/54 MHz (C
L
=30 pF)
— Burst access times of 9.3/11/13.5 ns at industrial
temperature range
— Synchronous latency of 49/56/69 ns
— Asynchronous random access times of 45/50/55 ns
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
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■
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29BDS128H/Am29BDS640H is a 128 or 64 Mbit, 1.8
Volt-only, simultaneous Read/Write, Burst Mode Flash mem-
ory device, organized as 8,388,608 or 4,194,304 words of 16
bits each. This device uses a single V
CC
of 1.65 to 1.95 V to
read, program, and erase the memory array. A 12.0-volt V
HH
on ACC may be used for faster program performance if de-
sired. The device can also be programmed in standard
EPROM programmers.
At 75 MHz, the device provides a burst access of 9.3 ns at
30 pF with a latency of 49 ns at 30 pF. At 66 MHz, the device
provides a burst access of 11 ns at 30 pF with a latency of
56 ns at 30 pF. At 54 MHz, the device provides a burst ac-
cess of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The
device operates within the industrial temperature range of
-40°C to +85°C. The device is offered in FBGA packages.
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into four
banks. The device can improve overall system performance
by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank, with zero latency. This releases the system from wait-
ing for the completion of program or erase operations.
The device is divided as shown in the following table:
Quantity
Bank
A
31
B
C
D
8
8
4 Kwords
96
96
31
15
48
48
15
32 Kwords
32 Kwords
32 Kwords
32 Kwords
128 Mb
8
64 Mb
8
Size
4 Kwords
The clock polarity feature provides system designers a
choice of active clock edges, either rising or falling. The ac-
tive clock edge initiates burst accesses and determines
when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The
hardware RESET# pin
terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read boot-up firm-
ware from the Flash memory device.
The host system can detect whether a program or erase op-
eration is complete by using the device status bit DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program
or erase cycle has been completed, the device automatically
returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The device also offers two types of data
protection at the sector level. When at V
IL
,
WP#
locks the
four highest and four lowest boot sectors.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power con-
sumption is greatly reduced in both modes.
AMD Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using
hot electron injection.
The VersatileIO™ (V
IO
) control allows the host system to set
the voltage levels that the device generates at its data out-
puts and the voltages tolerated at its data inputs to the same
voltage level that is asserted on the V
IO
pin.
The device uses Chip Enable (CE#), Write Enable (WE#),
Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with
minimal glue logic to a wide range of microprocessors/micro-
controllers for high performance read operations.
The burst read mode feature gives system designers flexibil-
ity in the interface to the device. The user can preset the
burst length and wrap through the same memory space, or
read the flash array in continuous mode.
2
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 8
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Device Bus Operations ....................................................11
Low V
CC
Write Inhibit .............................................................. 24
Write Pulse “Glitch” Protection ................................................ 24
Logical Inhibit .......................................................................... 24
Power-Up Write Inhibit ............................................................ 24
Table 8. CFI Query Identification String ......................................... 24
Table 9. System Interface String .................................................... 25
Table 10. Device Geometry Definition ........................................... 25
Table 11. Primary Vendor-Specific Extended Query ..................... 26
Table 12. Am29BDS128H Sector Address Table .......................... 27
Table 13. Am29BDS640H Sector Address Table .......................... 31
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................ 11
Requirements for Synchronous (Burst) Read Operation ........ 11
8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 12
Table 2. Burst Address Groups .......................................................12
Command Definitions . . . . . . . . . . . . . . . . . . . . . 33
Reading Array Data ................................................................ 33
Set Configuration Register Command Sequence ................... 33
Figure 3. Synchronous/Asynchronous State Diagram ................... 33
Read Mode Setting ................................................................. 33
Programmable Wait State Configuration ................................ 33
Table 14. Programmable Wait State Settings ................................ 34
Burst Suspend/Resume .......................................................... 12
Configuration Register ............................................................ 13
Reduced Wait-state Handshaking Option .............................. 13
Simultaneous Read/Write Operations with Zero Latency ....... 13
Writing Commands/Command Sequences ............................ 13
Accelerated Program Operation ............................................. 14
Autoselect Mode ..................................................................... 14
Table 3. Autoselect Codes (High Voltage Method) ........................15
Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................16
Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................17
Reduced Wait-state Handshaking Option ............................... 34
Table 15. Wait States for Reduced Wait-state Handshaking ........ 34
Standard Handshaking Option ................................................ 35
Table 16. Wait States for Standard Handshaking .......................... 35
Read Mode Configuration ....................................................... 35
Table 17. Read Mode Settings ....................................................... 35
Burst Active Clock Edge Configuration ................................... 35
RDY Configuration .................................................................. 35
Table 18. Configuration Register ................................................... 36
Reset Command ..................................................................... 36
Autoselect Command Sequence ............................................ 36
Table 19. Autoselect Data .............................................................. 37
Sector/Sector Block Protection and Unprotection .................. 17
Sector Protection .................................................................... 17
Selecting a Sector Protection Mode ....................................... 17
Persistent Sector Protection ................................................... 18
Persistent Protection Bit (PPB) ............................................... 18
Persistent Protection Bit Lock (PPB Lock) ............................. 18
Dynamic Protection Bit (DYB) ................................................ 18
Table 6. Sector Protection Schemes ...............................................19
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 37
Program Command Sequence ............................................... 37
Unlock Bypass Command Sequence ..................................... 37
Figure 4. Program Operation ......................................................... 38
Persistent Sector Protection Mode Locking Bit ...................... 19
Password Protection Mode ..................................................... 19
Password and Password Mode Locking Bit ........................... 20
64-bit Password ...................................................................... 20
Persistent Protection Bit Lock ................................................. 20
High Voltage Sector Protection .............................................. 20
Standby Mode ........................................................................ 20
Automatic Sleep Mode ........................................................... 21
RESET#: Hardware Reset Input ............................................. 21
Output Disable Mode .............................................................. 21
Figure 1. Temporary Sector Unprotect Operation........................... 21
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 22
Chip Erase Command Sequence ........................................... 38
Sector Erase Command Sequence ........................................ 38
Erase Suspend/Erase Resume Commands ........................... 39
Figure 5. Erase Operation.............................................................. 40
Password Program Command ................................................ 40
Password Verify Command .................................................... 40
Password Protection Mode Locking Bit Program Command .. 40
Persistent Sector Protection Mode Locking Bit Program Com-
mand ....................................................................................... 40
SecSi Sector Protection Bit Program Command .................... 41
PPB Lock Bit Set Command ................................................... 41
DYB Write Command ............................................................. 41
Password Unlock Command .................................................. 41
Figure 6. PPB Program Algorithm.................................................. 42
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 23
Factory-Locked Area (64 words) ............................................ 23
Table 7. SecSi
TM
Sector Addresses ...............................................23
PPB Program Command ........................................................ 43
All PPB Erase Command ........................................................ 43
Figure 7. PPB Erase Algorithm ...................................................... 44
Customer-Lockable Area (64 words) ...................................... 23
SecSi Sector Protection Bits ................................................... 23
Hardware Data Protection ...................................................... 23
Write Protect (WP#) ................................................................ 24
DYB Write Command ............................................................. 45
PPB Status Command ............................................................ 45
PPB Lock Bit Status Command .............................................. 45
DYB Status Command ............................................................ 45
Command Definitions ............................................................. 46
Table 20. Memory Array Command Definitions ............................ 46
Table 21. Sector Protection Command Definitions ....................... 47
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
3
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