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MT48G8M16LFB4-10IT

Description
Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8 X 8 MM, LEAD FREE, VFBGA-54
Categorystorage   
File Size2MB,65 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT48G8M16LFB4-10IT Overview

Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8 X 8 MM, LEAD FREE, VFBGA-54

MT48G8M16LFB4-10IT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeBGA
package instructionVFBGA, BGA54,9X9,32
Contacts54
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
access modeFOUR BANK PAGE BURST
Maximum access time7 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeS-PBGA-B54
JESD-609 codee1
length8 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA54,9X9,32
Package shapeSQUARE
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.00035 A
Maximum slew rate0.17 mA
Maximum supply voltage (Vsup)3.3 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width8 mm
Base Number Matches1
128Mb: x16, x32
MOBILE SDRAM
SYNCHRONOUS
DRAM
Features
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT auto
precharge, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial Array Self Refresh power-saving mode
OPTIONS
MARKING
LC
G
V
8M16
4M32
MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF,
MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF
MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC,
MT48V4M32LFF5
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/dramds
Figure 1: Pin Assignment (Top View)
54-Ball FBGA
1
A
B
C
D
E
F
G
H
J
V
SS
2
DQ15
3
V
SS
Q
4
5
6
7
V
DD
Q
8
DQ0
9
V
DD
DQ14
DQ13
V
DD
Q
V
SS
Q
DQ2
DQ1
DQ12
DQ11
V
SS
Q
V
DD
Q
DQ4
DQ3
DQ10
DQ9
V
DD
Q
V
SS
Q
DQ6
DQ5
DQ8
NC
V
SS
V
DD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC/A12
A11
A9
BA0
BA1
CS#
• V
DD
/V
DD
Q
3.3V/3.3V
3.0V/3.0V
1
2.5V/2.5V – 1.8V
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package/Ball out
54-ball FBGA (8mm x 9mm)
2
54-ball FBGA (8mm x 9mm)
2
Lead-Free
54-ball VFBGA (8mm x 8mm)
2
54-ball VFBGA (8mm x 8mm)
2
Lead-Free
90-ball FBGA (11mm x 13mm)
3
90-ball FBGA (11mm x 13mm)
3
Lead-Free
90-ball VFBGA (8mm x 13mm)
3
90-ball VFBGA (8mm x 13mm)
3
Lead-Free
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
• Temperature
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Extended (-25°C to +75°C)
NOTE:
A8
A7
A6
A0
A1
A10
V
SS
A5
A4
A3
A2
V
DD
Top View
(Ball Down)
8 Meg x 16
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column
Addressing
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
4 Meg x 32
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
FF
BF
F4
B4
FC
BC
F5
B5
-8
-10
None
IT
XT
Part Number Example:
Table 1:
MT48V8M16LFFF-8
Key Timing Parameters
ACCESS TIME
CL=1*
CL=2*
CL=3*
t
RCD
t
RP
SPEED
CLOCK
GRADE FREQUENCY
1. Check with factory for configuration and availability.
2. x16 Only.
3. x32 Only.
-8
-10
-8
-10
-8
-10
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
19ns
22ns
8ns
8ns
7ns
7ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
*CL = CAS (READ) latency
09005aef8071a76b
MobileY95W_3V_1.fm - Rev. H 10/03 EN
1
©2001 Micron Technology, Inc. All rights reserved.

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