CAT24WC33/65
32K/64K-Bit I
2
C Serial CMOS EEPROM
FEATURES
I
400 KHz I
2
C Bus Compatible*
I
1.8 to 5.5 Volt Read and Write Operation
I
Cascadable for up to Eight Devices
I
32/64-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
8-Pin DIP or 8-Pin SOIC
I
Schmitt Trigger Inputs for Noise Protection
I
Commercial, Industrial and Automotive Tem-
perature Ranges
I
Write Protection
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
–Bottom 1/4 Array Protected When WP at V
IH
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E
2
PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
DIP Package (P, L)
SOIC Package (J, W, K, X)
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
i
D
VSS
c
s
Ground
u
n
i
t
n
o
VCC
WP
SCL
VCC
VSS
BLOCK DIAGRAM
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
EXTERNAL LOAD
d
e
START/STOP
LOGIC
CONTROL
LOGIC
a
P
s
t
r
COLUMN
DECODERS
256
SDA
WORD ADDRESS
BUFFERS
SDA
E
2
PROM
XDEC 128/256 128/256 X 256
WP
Function
DATA IN STORAGE
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1049, Rev. D
CAT24WC33/65
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Max.
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
i
D
Output Low Voltage (V
CC
= +3.0V)
Output Low Voltage (V
CC
= +1.8V)
c
s
u
n
i
t
n
o
Limits
Typ.
Min.
–1
V
CC
x 0.7
d
e
Max.
3
1
10
10
µA
µA
µA
V
V
V
V
0.4
0.5
a
P
Units
Volts
mA
Cycles/Byte
Years
s
t
r
Units
mA
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
V
CC
x 0.3
V
CC
+ 0.5
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Doc. No. 1049, Rev. D
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC33/65
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
Symbol
F
SCL
T
I
(1)
CAT24WCXX
2.5V-5.5V
Min.
Max.
100
200
3.5
4.7
4
4.5V-5.5V
Min.
Max.
400
Parameter
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK
Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
Min.
Max.
10 0
200
3.5
t
AA
t
BUF
(1)
4.7
4
4.7
4
4.7
0
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
SDA and SCL Rise Time
SDA and SCL Fall Time
Data Out Hold Time
Stop Condition Setup Time
Power-Up Timing
(1)(2)
Symbol
t
PUR
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
t
WR
i
D
t
PUW
c
s
Power-Up to Read Operation
Power-Up to Write Operation
u
n
i
t
n
o
50
1
4
100
30 0
d
e
4
4.7
0
50
4
100
4.7
a
P
1.2
0.6
1.2
0.6
0.6
0
50
0.6
100
s
t
r
Units
kHz
ns
200
1
µs
µs
µs
µs
µs
µs
ns
ns
0.3
300
µs
ns
µs
ns
1
300
Parameter
Max.
1
1
Units
ms
ms
Parameter
Write Cycle Time
Min.
Typ.
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1049, Rev. D
CAT24WC33/65
FUNCTIONAL DESCRIPTION
The CAT24WC33/65 supports the I
2
C Bus data trans-
mission protocol. This Inter-Integrated Circuit Bus proto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC33/65
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These pins are hardwired or left unconnected (for hard-
ware compatibility with CAT24WC16). When hardwired,
up to eight CAT24WC33/65s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
Figure 1. Bus Timing
tF
tLOW
tHIGH
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFH for 24WC33) is write protected . When left floating,
memory is unprotected.
tR
tLOW
SCL
tSU:STA
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
SDA
i
D
c
s
SCL
u
n
i
t
n
o
tHD:STA
tHD:DAT
tAA
tDH
tSU:DAT
d
e
a
P
tSU:STO
tBUF
s
t
r
5020 FHD F03
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
START BIT
STOP BIT
5020 FHD F05
Doc. No. 1049, Rev. D
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC33/65
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
compare to the hardwired input pins, A2, A1 and A0. The
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC33/65 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC33/65 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv-
ing each 8-bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 32K/64K devices may
to be connected to the same bus. These bits must
Figure 4. Acknowledge Timing
i
D
DATA OUTPUT
FROM TRANSMITTER
c
s
SCL FROM
MASTER
u
n
i
t
n
o
1
START
When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.
d
e
8
a
P
9
s
t
r
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
5027 FHD F07
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1049, Rev. D
FPGA/CPLD
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