IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
• Easy memory expansion with
CE
and
OE
op-
tions
•
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
V
DD
1.65V to 2.2V (IS61WV51216ALL)
speed = 20ns for V
DD
1.65V to 2.2V
V
DD
2.4V to 3.6V (IS61/64WV51216BLL)
speed = 10ns for V
DD
2.4V to 3.6V
speed = 8ns for V
DD
3.3V + 5%
• Packages available:
– 48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
OCTOBER 2009
DESCRIPTION
The
ISSI
IS61WV51216ALL/BLL and IS64WV51216BLL
are high-speed, 8M-bit static RAMs organized as 512K
words by 16 bits. It is fabricated using
ISSI
's high-perform-
ance CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-perfor-
mance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The device is packaged in the JEDEC standard 44-pin
TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
1
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
TRUTH TABLE
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Mode
Not Selected
Output Disabled
Read
V
DD
Current
I
SB
1
, I
SB
2
I
CC
I
CC
Write
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
DD
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
V
DD
Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
DD
+ 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
京公网安备 11010802033920号
EEWORLD
