CY7C1325F-133BGI datasheet, PDF

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CY7C1325F-133BGI: DescriptionCache SRAM, 256KX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119; Categorystorage; File Size448KB，17 Pages; ManufacturerCypress Semiconductor

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CY7C1325F-133BGI Overview

Cache SRAM, 256KX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

CY7C1325F-133BGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	14 X 22 MM, 2.40 MM HEIGHT, BGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	6.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.225 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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CY7C1325F

4-Mb (256K x 18) Flow-Through Sync SRAM

Features

• 256K X 18 common I/O

• 3.3V –5% and +10% core power supply (V

)

• 2.5V or 3.3V I/O supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.0 ns (100-MHz version)

— 11.0ns (66-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel



Pentium



interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP and 119-ball

BGA packages

• “ZZ” Sleep Mode option

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:B]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1325F allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1325F operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Functional Description

[1]

The CY7C1325F is a 262,144 x 18 synchronous cache RAM

designed to interface with high-speed microprocessors with

Logic Block Diagram

A0,A1,A

MODE

ADDRESS

A[1:0]

ADV

CLK

BURST Q1

COUNTER AND

LOGIC

CLR

ADSC

ADSP

,DQP

WRITE REGISTER

,DQP

WRITE DRIVER

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

BWE

,DQP

WRITE REGISTER

,DQP

WRITE DRIVER

INPUT

REGISTERS

DQs

DQP

ENABLE

SLEEP

CONTROL

Note:

1. For best–practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05215 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised January 13, 2004

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