ISL3873A
TM
Data Sheet
September 2001
File Number
8015.2
Wireless LAN Integrated Medium Access
Controller with Baseband Processor
The Intersil ISL3873A Wireless LAN
Integrated Medium Access Controller
with Integrated Baseband Processor
is part of the PRISM® 2.4GHz radio
chip set. The ISL3873A directly interfaces with the Intersil’s
IF QMODEM (HFA3783). Adding Intersil’s RF/IF Converter
(ISL3685) and Intersil’s Power Amp (HFA3983) offers the
designer a complete end-to-end WLAN Chip Set solution.
Protocol and PHY support are implemented in firmware thus,
supporting customization of the WLAN solution.
Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgment, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handled without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.
The ISL3873A has on-board A/Ds and D/A for analog I and
Q inputs and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling
capability, are available along with Complementary Code
Keying to provide a variety of data rates. Both Receive and
Transmit AGC functions with 7-bit AGC control obtain
maximum performance in the analog portions of the
transceiver.
Built-in flexibility allows the ISL3873A to be configured
through a general purpose control bus, for a range of
applications. The ISL3873A is housed in a thin plastic BGA
package suitable for PCMCIA board applications.
The ISL3873A is designed to provide maximum
performance with minimum power consumption. External pin
layout is organized to provide optimal PC board layout to all
user interfaces including PCMCIA and USB.
Features
• PCMCIA Host Interface and compatibility with USB V1.1.
• New Start Up Modes Allow the PCMCIA Card Information
Structure to be Initialized From a Serial EEPROM. This
Allows Firmware to be Downloaded from the Host,
Eliminating the Parallel Flash Memory Device
• Firmware Can be Loaded from Serial Flash Memory
• Zero Glue Connection to 16-Bit Wide SRAM Devices
• Low Frequency Crystal Oscillator to Maintain Time and
Allow Baseband Clock Source to Power off During Sleep
Mode
• Improved Performance of Internal WEP Engine
• Improvements to Debug Mode Support Tracing Execution
From on Chip Memory
• Programmable MBUS Cycle Extension Allows Accessing
of Slow Memory Devices Without Slowing the Clock
• Complete DSSS Baseband Processor
• RAKE Receiver with Decision Feedback Equalizer
• Processing Gain. . . . . . . . . . . . . . . . . . . . .FCC Compliant
• Programmable Data Rate . . . . . . . .1, 2, 5.5, and 11Mbps
• Ultra Small Package. . . . . . . . . . . . . . . . . . . . . 14 x 14mm
• Single Supply Operation . . . . . . . . . . . . . . . . 2.7V to 3.6V
• Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK
• Supports Full or Half Duplex Operations
• On-Chip A/ D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
• Targeted for Multipath Delay Spreads 125ns at 11Mbps,
250ns at 5.5Mbps
• Supports Short Preamble and Antenna Diversity
Applications
• PC Card Wireless LAN Adapters
• USB and PCMCIA Wireless LAN Adapters
• PCN / Wireless PBX / Wireless Local Loop
• High Data Rate Wireless LAN Systems Targeting IEEE
802.11b Standard
• Wireless LAN Access Points and Bridge Products
• Spread Spectrum WLAN RF Modems
Ordering Information
PART
NUMBER
ISL3873AIK
ISL3873AIK-TK
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
PACKAGE
192 BGA
PART
NUMBER
V192.14x14
• TDMA or CSMA Packet Protocol Radios
• PCI Wireless LAN Cards (Using Ext. Bridge Chip)
• ISA, ISA PNP WLAN Cards
Tape and Reel 1000 Units /Reel
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
PRISM® is a registered trademark of Intersil Americas Inc.
PRISM and design is a trademark of Intersil Americas Inc.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
ISL3873A
Simplified Block Diagram
HOST
COMPUTER
DATA
ADDRESS
CONTROL
USB
ISL3873A
PC CARD
HOST
INTERFACE
USB
HOST
INTERFACE
1
1
7
IF
DAC
6
I ADC
DEMOD
WEP
ENGINE
6
Q ADC
PHY
INTERFACE
(MDI)
SERIAL
CONTROL
(MMI)
DATA I/O
RXQ±
THRESH.
DETECT
ANT_SEL
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
RXI±
PRISM RADIO
RF SECTION
MICRO-
PROGRAMMED
MAC ENGINE
AGC
CTL
ON-CHIP
ROM
MEMORY
CONTROLLER
ON-CHIP
RAM
I/O
V
REF
TXI±
6
MOD
6
I DAC
TXQ±
Q DAC
TX
DAC
TX
ADC
TX_IF_AGC
TX_AGC_IN
TX
ALC
7
6
RADIO AND SYNTH
SERIAL CONTROL
MEDIUM ACCESS
CONTROLLER
BASEBAND PROCESSOR
ADDRESS
DATA
SELECT
EXTERNAL
SRAM AND
FLASH
MEMORY
44MHz CLOCK
SOURCE
†
†
THE ISL3873A MUST BE SUPPLIED WITH A
SEPARATE CLOCK WHEN USB IS USED.
2
ISL3873A
ISL3873A Signal Descriptions
Host Interface Pins
PIN NAME
HA0-9
HCE1-
HCE2-
HD0-15
HINPACK-
HIORD-
HIOWR-
HRDY/HIREQ-
PIN I/O TYPE
5V tol, CMOS, Input, 50K Pull Down
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
5V tol, BiDir, 2mA, 50K Pull Down
CMOS Output, 2mA
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
CMOS Output, 4mA
DESCRIPTION
Host PC Card Address Input, Bits 0 to 9
Host PC Card Select, Low Byte
Host PC Card Select, High Byte
Host PC Card Data Bus, Bit 0 to 15
Host PC Card I/O Decode Confirmation
Host PC Card I/O Space Read Strobe
Host PC Card I/O Space Write Strobe
Host PC Card interrupt Request (I/O Mode), also used as PC Card
Ready (Memory Mode) output which is asserted to indicate card
initialization is complete
Host PC Card Memory Attribute Space Output Enable
Host PC Card Attribute Space Select
Hardware Reset. Self-asserted by internal pull-up at power-on. Clock
signal CLKIN or XTALIN must be available before negation of Reset.
Value of MD[15..0] copied to MDIR[15..0] and various control register
bits on the first MCLK following release of Reset
Host PC Card Status Change
Host Wait, asserted to indicate data transfer not complete and to force
force host bus wait states
Host PC Card Memory Attribute Space Write Enable
USB INTERFACE PINS
PIN NAME
USB+
USB-
USB_DETECT
PIN I/O TYPE
CMOS BiDir, 2mA, (Also USB Transceiver)
CMOS BiDir, 2mA, (Also USB Transceiver)
Input, 5V tolerant, pull-down
DESCRIPTION
USB, MBUS Address Bit 20, or I/O as PL5
USB, MBUS Address Bit 21, or I/O as PL6
Sense USB VBUS to indicate cable attachment
Memory Interface Pins
PIN NAME
MUBE- / MA0 /
MWEH-
MA1-18
PL4-MA19
MLBE-
MOE-
MWE- / MWEL-
RAMCS-
NVCS-
MD0-7
MD8-15
PIN I/O TYPE
CMOS TS Output, 2mA
CMOS TS Output, 2mA
CMOS BiDir, 2mA
CMOS TS Output, 2mA, 50K Pull Up
CMOS TS Output, 2mA
CMOS TS Output, 2mA
CMOS TS Output, 2mA
CMOS TS Output, 2mA
5V tol, CMOS, BiDir, 2mA, 100K Pull Up
5V tol, CMOS, BiDir, 2mA
50K Pull-Downs on MD15, MD14, MD13, MD11,
MD10, MD09
50K Pull-Ups MD12, MD08
DESCRIPTION
MBUS Upper Byte Enable for x16 Memory; MBUS Address Bit 0 (byte)
for x8 Memory; High Byte Write Enable for 2 x8 Memories
MBUS Address Bits 1 to 18
MBUS Address Bit 19
MBUS Lower Byte Enable, or I/O as PM2
Memory Output Enable
Low (or only) Byte Memory Write Enable
RAM Select
NV Memory Select
MBUS Low Data Byte, Bits 0 to 7
MBUS High Data Byte, Bits 8 to 15
Default power up states are defined by pull-up and pull-down internal
resistors as shown. Device defaults to external EEPROM for boot up
mode. Using external 10K resistors, configure these pins according to
Table 4 to change power-up configuration
HOE-
HREG-
RESET
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, ST Input, 50K Pull Up
HSTSCHG-
HWAIT-
HWE-
CMOS Output, 4mA
CMOS Output, 4mA
5V tol, CMOS Input, 50K Pull Up
3
ISL3873A
MAC Radio Interface and General Purpose Port Pins
PIN NAME
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK7
PL3
PL7
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA, ST, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA, Pull Down
PIN I/O TYPE
PE1
LE_IF
LED1
RADIO_PE
LE_RF
SYNTHCLK
SYNTHDATA
PA_PE
PE2
CAL_EN
TR_SW_BAR
TR_SW
DESCRIPTION OF FUNCTION
(IF OTHER THAN I/O PORT)
SERIAL EEPROM PORT PINS
PIN NAME
PJ0
PJ1
PJ2
TCLKIN (CS_)
PIN NAME
CLKIN
XTALIN
XTALOUT
CLKOUT
BBP_CLK
PIN I/O TYPE
CMOS BiDir
CMOS BiDir, 50K Pull Down
CMOS BiDir, 50K Pull Down
CMOS BiDir
PIN I/O TYPE
CMOS Input, 50K Pull Down
Analog Input
CMOS Output, 2mA
CMOS, TS Output, 2mA
Input
SCLK, Serial Clock
SD, Serial Data Out
MISO, Serial Data IN
CS_, Chip Select
Clocks Port Pins
DESCRIPTION
External Clock Input to MCLK prescaler (at >= 2X Desired MCLK
Frequency, Typically 44-48MHz)
32.768kHz Crystal Input
32.768kHz Crystal Output
Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0)
Baseband Processor Clock. The nominal frequency for this clock is
44MHz. This is used internally to generate divide by 2 and 4 for the
transceiver clock
Baseband Processor Receiver Port Pins
PIN NAME
RX_IF_AGC
RX_RF_AGC
RX_IF_DET
RXI,
±
RXQ,
±
PIN I/O TYPE
O
O
I
I
I
Analog drive to the IF AGC control
Drive to the RF AGC stage attenuator. CMOS digital
Analog input to the receive power A/D converter for AGC control
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-
Baseband Processor Transmitter Port Pins
PIN NAME
TX_AGC_IN
TX_IF_AGC
TXI
±
TXQ
±
PIN I/O TYPE
I
O
O
O
DESCRIPTION
Input to the transmit power A/D converter for transmit AGC control
Analog drive to the transmit IF power control
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-
DESCRIPTION
DESCRIPTION
4
ISL3873A
Misc Control Port Pins
PIN NAME
ANTSEL
PIN I/O TYPE
O
DESCRIPTION
The antenna select signal changes state as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode. This is a
complement for ANTSEL (pin 40) for differential drive of antenna switches
The antenna select signal changes state as the receiver switches from antenna to
antenna during the acquisition process in the antenna diversity mode. This is a
complement for ANTSEL (pin 39) for differential drive of antenna switches
Factory level test pin. This pin must be pulled low with a 10K resistor.
Compensation Capacitor
Compensation Capacitor
Compensation Resistor
Compensation Resistor
Debug factory test signals. Do not connect
Power Port Pins
PIN NAME
V
DDA
V
DD
SUPPLY5V
V
SSA
V
sub
GND
VREF
IREF
PIN I/O TYPE
Power
Power
Power
Ground
Ground
Ground
Input
Input
DESCRIPTION
DC Power Supply 2.7 - 3.6V (Not Hardwired Together on Chip)
DC Power Supply 2.7 - 3.6V
5V Tolerant DC Power Supply
Analog Ground
Analog Ground
Digital Ground
Voltage Reference for A/D’s and D/A’s
Current Reference for internal ADC and DAC devices. Requires 12K resistor to ground.
ANTSEL
O
TestMode
CompCap1
CompCap2
CompRes1
CompRes2
DBG(0-4)
I/O
I
I
I
I
I/O
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.
ISL3873A Pin Number Assignments
PIN NUMBER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
SIGNAL NAME
NC
MA10
MA13
MA16
GND
PL4_MA19
DBG2
V
DD
HD3
HCE2
GND
HD15
HA9
V
DD
HA6
NC
D1
D2
D3
D4
D5
D6
B1
V
DD
D7
MA3
MA8
MA7
MA14
MA17
DBG0
GND
H1
H2
H3
V
DD
MLBE
MD11
PIN NUMBER
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
SIGNAL NAME
HD4
HD6
HD14
HD11
HD7
HA7
GND
DBG3
NC
RESET
G1
G2
G3
G4
G13
G14
G15
G16
MD12
MD14
V
DD
MA2
GND
HSTSCHG
HD0
BBP_CLK
M1
M2
M3
M4
M13
M14
M15
MD5
V
DD
GND
MD6
V
DDA
COMPCAP1
GND
PIN NUMBER
F4
F13
F14
F15
F16
SIGNAL NAME
MA5
HD9
HD10
HA2
HA1
L1
L2
L3
L4
L13
L14
L15
L16
MD8
MD7
MD10
MD9
GND
RX_RF_AGC
ANT_SEL
ANT_SEL
PIN NUMBER
K16
SIGNAL NAME
V
DD
5
京公网安备 11010802033920号
EEWORLD
