PI6C2401
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Phase-Locked Loop Clock Driver
Product Features
•
High-Performance Phase-Locked-Loop Clock Distribution for
Networking, ATM, 100/134 MHz Registered DIMM Synchro-
nous DRAM modules for server/workstation/PC applications
•
Zero Input-to-Output delay
•
Low jitter: Cycle-to-Cycle jitter ± 100ps max.
•
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
•
Operates at 3.3V V
CC
•
Packaged in Plastic 8-pin SOIC Package (W)
Pb-free and Green Available
•
Wide range of Clock Frequencies
Product Description
The PI6C2401 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Application
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-
to-device skew introduced can significantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer . As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
CLK_IN
FB_IN
S
CLK_OUT
PLL
CLK_IN
AV
CC
AGND
CLK_OUT
1
2
3
4
8-Pin
W
8
7
6
5
FB_IN
V
CC
GND
S
Feedback
Control Input
S
Output Source
PLL
CLK_IN
PLL Shutdown
N
Y
Reference
Clock
Signal
Zero Delay
Buffer
PI6C2401
V
CLK_OUT
18 Output
Non-Zero
Delay
Buffer
1
17
0
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clocks Signal and 17 Outputs
PS8419C
01/12/05
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PI6C2401
Phase-Locked Loop Clock Driver
Pin Functions
Pin Name
CLK_IN
AV
CC
AGND
CLK_OUT
Pin Numbe r
1
2
3
4
Type
I
Power
Ground
O
De s cription
Reference Clock input. CLK_IN allows spread spectrum clock input.
Analog power supply.
Analog ground.
Clock outputs. The output provides low- skew copies of CLK_IN
and has an embedded series- damping resistor.
Control Input S. S is used to bypass the PLL for test purposes.
When S is strapped to ground, PLL is bypassed and CLK_IN
is buffered directly to the device outputs.
Ground.
Power supply.
Feedback input. FB
IN
provides the feedback signal to the internal PLL.
S
GND
V
CC
FB_IN
5
6
7
8
I
Ground
Power
I
DC Specifications
(Absolute maximum ratings over operating free-air temperature range)
Symbol
V
I
V
O
VI
_
DC
IO
_
DC
Power
T
STG
Input voltage range
Output voltage range
DC input voltage
DC output current
Maximum power dissipation at T
A
= 55
o
C in still air
Storage temperature
- 65
−
0.5
V
CC
+ 0.5
V
+5.0
100
1.0
150
mA
W
o
C
Parame te r
M in.
M ax.
Units
Note:
Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Parame te r
I
CC
C
I
C
O
Te s t Conditions
V
I
= V
CC
or GND; I
O
= 0
(1)
V
I
= V
CC
or GND
V
CC
3.6V
M in.
Typ.
M ax.
10
Units
µA
pF
4
3.3V
6
V
O
= V
CC
or GND
Note:
1. Continuous output current
2
PS8419C
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2401
Phase-Locked Loop Clock Driver
Recommended Operating Conditions
Symbol
V
C C
V
IH
V
IL
V
I
T
A
Supply voltage
High level input voltage
Low level input voltage
Input voltage
Operating free- air temperature
0
0
Parame te r
M in.
3.0
2.0
V
0.8
V
C C
70
ºC
M a x.
3.6
Units
Electrical Characteristics
(Over recommended operating free-air temperature range Pull Up/Down Currents, V
CC
= 3.0V)
Symbol
I
O H
Parame te r
Pull- up current
Condition
V
O U T
= 2.4V
V
O U T
= 2.0V
M in.
M ax.
−
12
−
18
Units
mA
I
O L
Pull- down current
V
O U T
= 0.8V
V
O U T
= 0.55V
18
12
AC Specifications
Timing Requirements
(Over recommended ranges of supply voltage and operating free-air temperature)
Symbol
F
CLOCK
D
CYI
Parame te r
Clock frequency
Input clock duty cycle
Stabilization Time after power up
M in.
25
40
M a x.
134
60
1
Units
MHz
%
ms
Switching Characteristics
(Over recommended ranges of supply voltage and operating free-air temperature, C
L
=30pF)
V
CC
= 3.3V ± 0.3V, 0-70 °C
Parame te r
tphase error without jitter
From
CLK_IN
↑
at 100 MHz
and 66 MHz
At 100 MHz and 66 MHz
To
FB_IN
↑
M in.
Typ.
M a x.
+175
ps
Jitter, cycle- to- cycle
Duty cycle
tr, rise- time, 0.4V to 2.0V
tf, fall- time, 2.0V to 0.4V
Note:
These switching parameters are guaranteed by design.
3
PS8419C
01/12/05
Units
CLK_OUT
–150
35
+150
65
1. 0
ns
1.1
%
CLK_OUT
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2401
Phase-Locked Loop Clock Driver
Package Mechanical Information
Plastic 8-pin SOIC Package
8
.149
.157
3.78
3.99
.0099
.0196
0.25
x 45˚
0.50
1
.189
.196
.016
.026
0.406
0.660
REF
4.80
5.00
1.35
1.75
SEATING PLANE
0-8˚
.0075
.0098
0.40 .016
1.27 .050
0.19
0.25
.053
.068
.2284
.2440
5.80
6.20
.050
BSC
1.27
.013 0.330
.020 0.508
.0040 0.10
.0098 0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Orde ring Code
PI6C2401W
PI6C2401WE
Package Code
W
W
Package Type
8- pin 150- mil SOIC
Pb- free and Green
8- pin 150- mil SOIC
Ope rating Range
Commercial
Commercial
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
4
PS8419C
01/12/05
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