TO 19 OTHER CHANNELS
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Product Features
•
PI74AVC
+
16836 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
•
True ±24mA Balanced Drive @ 3.3V
•
I
OFF
supports partial power-down operation
•
3.6V I/O Tolerant inputs and outputs
•
Meets PC133 SDRAM Registered DIMM Specifications
• All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise without
degrading propagation delay
• Industrial operation at –40°C to +85°C
• Available Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 20-bit PI74AVC+16836 universal bus driver is designed
for 1.65V to 3.6V Vcc operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is HIGH,
the A data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state, but all the inputs are enabled and data is capable
of being stored in the register.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
1
OE
56
CLK
LE
29
A1
55
1D
C1
CLK
2
Y1
1
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
Vcc
De s cription
Output Enable Input (Active LOW)
Latch Enable (Active LOW)
Clock Input
Data Input
Data Output
Ground
Power
Truth Table
(1)
Inputs
OE
H
L
L
L
L
L
LE
X
L
L
H
H
H
CLK
X
X
X
↑
↑
L or H
A
X
L
H
L
H
X
Z
L
H
L
H
Yo
( 2 )
Outputs
Y
Pin Configuration
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
V
CC
Y17
Y18
GND
Y19
Y20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
56-Pin
43
A, K
42
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
V
CC
A17
A18
GND
A19
A20
LE
Note:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑
= Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established.
41
40
39
38
37
36
35
34
33
32
31
30
29
2
PS8511A
02/06/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC ............................................................................................
–0.5V to +4.6V
Input voltage range, V
I ....................................................................................................
–0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, V
O(1) ............................................................
–0.5V to +4.6V
Voltage range applied to any output in the
high or low state, V
O(1,2) ........................................................................................
–0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................................................ –50mA
Output clamp current, I
OK
(V
O
<0) ...................................................................... –50mA
Continuous output current, I
O ......................................................................................................
±50mA
Continuous current through each V
CC
or GND ................................................. ±100mA
Package thermal impedance,
θ
JA
(3)
: package A .................................................... 64°C/W
package K ................................................... 48°C/W
Storage Temperature range, T
stg ..............................................................................
–65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
(1)
M in.
Operating
V
CC
Supply Voltage
Data retention only
V
CC
= 1.2V
V
IH
High- level Input Voltage
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.2V
V
IL
Low- level Input Voltage
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
I
V
O
Input Voltage
Active State
Output Voltage
3- State
V
CC
= 1.65V to 1.95V
I
OH
High- level output current
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.65V to 1.95V
I
OL
Low- level output current
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
∆t∆
v Input transition rise or fall rate
T
A
Operating free- air temperature
V
CC
= 1.65V to 3.6V
–40
0
0
0
1.65
1.2
V
CC
0.65 x V
CC
1.7
2
Gnd
0.35 x V
CC
0.7
0.8
3.6
V
CC
3.6
–6
– 12
– 24
6
12
24
5
85
ns/V
°C
mA
V
M ax.
3.6
Units
Notes:
1. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, T
A
= –40°C
+85°C)
Parame te rs
Te s t Conditions
(1)
I
O H
= –100
µA
I
O H
= –6mA
V
IH
= 1.07V
V
IH
= 1.7V
I
O H
= –12mA
I
O H
= –24mA
V
IH
= 2V
I
O L
= 100
µA
V
IH
= 0.57V
I
O L
= 6mA
V
IH
= 0.7V
I
O L
= 12mA
I
O L
= 24mA
V
IH
= 0.8V
V
I
= V
C C
or GND
V
I
or V
O
= 3.6V
V
I
= V
C C
or GND
V
O
= V
C C
or GND I
O
= 0
V
CC
1.65V to 3.6V
1.65V
2.3V
3V
1.65V to 3.6V
1.65V
2.3V
3V
3.6V
0
3.6V
3.6V
2.5V
3.3V
2.5V
3.3V
2.5V
3.3V
M in.
V
C C
–0.2V
1.2
1.75
2.0
0.2
0.45
0.55
0.8
±2.5
±10
±10
40
4
4
6
6
8
8
M ax.
Units
V
O H
V
V
O L
I
I
I
O F F
I
O Z
I
C C
Control Inputs
µA
Control Inputs
C
I
Data Inputs
C
O
Outputs
V
O
= V
C C
or GND
V
I
= V
C C
or GND
pF
Note:
Typical values are measured at T
A
= 25°C.
4
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Vcc = 1.2V
Vcc = 1.5V
±0.1V
Vcc = 1.8V
±0.15V
M in.
M ax.
180
2.0
2.0
1. 4
1.4
1. 4
1. 0
1. 0
1.2
1.2
1.2
1.2
1.2
0.8
0.8
Vcc = 2.5V
±0.2V
M in.
M ax.
180
1.0
1.0
1.0
1.0
1.0
0.6
0.6
ns
Vcc = 3.3V
±0.3V
M in.
M ax.
18 0
Units
MHz
M in. M ax. M in. M ax.
fclock
t
w
Pulse Duration
Clock Frequency
LE Low
CLK High or Low
Data before CLK
↑
t
su
Setup Time
Data before CLK High
LE
↑
CLK Low
Data after CLK
↑
t
h
Hold Time
Data
after LE
↑
CLK High
or Low
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
V
CC
= 1.2V
V
CC
= 1.5V
±0.1V
M ax.
V
CC
= 1.8V
±0.15V
M in.
180
A
1.0
1.0
Y
1.0
1. 5
1. 5
4.5
5.0
4.5
5.5
5.0
M ax.
V
CC
= 2.5V
±0.2V
M in.
180
0.8
0.8
0.8
1.0
1.0
3.0
3.3
3.0
4.5
4.5
M ax.
V
CC
= 3.3V
±0.3V
M in.
180
0.7
0.7
0.7
1.0
1.0
2.4
2.5
2.5
4.0
4.0
ns
M ax.
MHz
Units
M in. M ax. M in.
f
max
t
pd
LE
CLK
t
en
t
dis
OE
OE
Operating Characteristics, T
A
= 25°C
Parame te rs
Te s t
Conditions
Outputs Enabled
C
pd
Power Dissipation Capacitance
Outputs Disabled
V
CC
= 1.8V
±0.1V
Typical
C
L
= 0pF,
f = 10 MHz
48
25
V
CC
= 2.5V
±0.2V
Typical
50
28
V
CC
= 3.3V
±0.3V
Typical
55
pF
32
Units
5
PS8511A
02/06/01
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