PDU10256H
8-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU10256H)
FEATURES
•
•
•
•
•
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
GND
ENB
1
2
48
47
GND
OUT
data
3
®
delay
devices,
inc.
PACKAGES
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6
A0
VEE
GND
7
8
9
42
41
40
A1
A2
GND
PIN DESCRIPTIONS
IN
OUT
A0-A7
ENB
VEE
GND
Signal Input
Signal Output
Address Bits
Output Enable
-5 Volts
Ground
A3
VEE
GND
IN
15
16
17
19
34
33
32
A4
A5
GND
PDU10256H-xxC5 SMD
PDU10256H-xxMC5 Mil SMD
A6
VEE
23
24
25
A7
PDU10256H-xx DIP
PDU10256H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TD
A
, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device, and TD
0
is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
•
•
•
•
•
•
•
Total programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
12ns typical
Setup time and propagation delay:
Address to input setup (T
AIS
):
3.6ns
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0° to 70° C
Temperature coefficient:
100PPM/°C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
±
5%
Power Dissipation:
925mw typical (no load)
Minimum pulse width:
16% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU10256H-.5
PDU10256H-1
PDU10256H-2
PDU10256H-3
PDU10256H-4
PDU10256H-5
PDU10256H-6
PDU10256H-8
PDU10256H-10
Incremental Delay
Per Step (ns)
0.5
±
0.3
1.0
±
0.5
2.0
±
0.5
3.0
±
1.0
4.0
±
1.0
5.0
±
1.5
6.0
±
1.5
8.0
±
2.0
10.0
±
2.0
Total
Delay (ns)
127.5
±
6.4
255
±
12.8
510
±
25.5
765
±
38.2
1020
±
51.0
1275
±
63.8
1530
±
76.5
2040
±
102
2550
±
128
©
1997 Data Delay Devices
NOTE: Any dash number between .5 and 10
not shown is also available.
Doc #97047
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU10256H
APPLICATION NOTES
ADDRESS UPDATE
The PDU10256H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T
OAX
, is required before the address lines can
change. This time is given by the following
relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the
AC
Characteristics
table. The
recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The
suggested
conditions are
those for which signals will propagate through the
unit without significant distortion. The
absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
A7-A0
T
AENS
ENB
T
ENIS
IN
TD
A
OUT
A
i-1
T
OAX
T
AIS
A
i
PW
IN
T
DISH
PW
OUT
T
DISO
Figure 1: Timing Diagram
Doc #97047
12/17/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
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