PDU1032H
5-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1032H)
FEATURES
•
•
•
•
•
Digitally programmable in 32 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced &
buffered
Fits 32-pin DIP socket
GND
ENB
1
2
32
31
PACKAGES
GND
OUT
A0
VEE
GND
IN
7
8
9
11
26
25
24
A1
A2
GND
A3
VEE
15
16
17
A4
NC
NC
OUT
GND
ENB
NC
NC
NC
GND
ENB
NC
NC
NC
NC
NC
NC
NC
GND
ENB
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
A2
A1
VEE
A0
NC
NC
A4
VEE
A3
NC
NC
NC
NC
NC
NC
NC
VEE
NC
PDU1032H-xx DIP
PDU1032H-xxM Mil DIP
PDU1032H-xxC5 SMD
PDU1032H-xxMC5 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU1032H-series device is a 5-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends
on the address code (A4-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
PIN DESCRIPTIONS
IN
OUT
A0-A4
ENB
VEE
GND
Signal Input
Signal Output
Address Bits
Output Enable
-5 Volts
Ground
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced
into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
•
•
•
•
•
•
•
•
Total programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
5.5ns typical for dash numbers
up to 5, greater for larger #’s
Setup time and propagation delay:
Address to input setup (T
AIS
):
3.6ns
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0° to 70° C
Temperature coefficient:
100PPM/°C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
±
5%
Power Dissipation:
615mw typical (no load)
Minimum pulse width:
20% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU1032H-.5
PDU1032H-1
PDU1032H-2
PDU1032H-3
PDU1032H-4
PDU1032H-5
PDU1032H-6
PDU1032H-8
PDU1032H-10
PDU1032H-12
PDU1032H-15
PDU1032H-20
Incremental Delay
Per Step (ns)
0.5
±
0.3
1.0
±
0.5
2.0
±
0.5
3.0
±
1.0
4.0
±
1.0
5.0
±
1.0
6.0
±
1.0
8.0
±
1.0
10.0
±
1.5
12.0
±
1.5
15.0
±
1.5
20.0
±
2.0
Total
Delay (ns)
15.5
±
2.0
31
±
2.0
62
±
3.1
93
±
4.6
124
±
6.2
155
±
7.8
186
±
9.3
248
±
12.4
310
±
15.5
372
±
18.6
465
±
23.2
620
±
31.0
2003
Data Delay Devices
NOTE: Any dash number between .5 and 20
not shown is also available.
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU1032H
APPLICATION NOTES
ADDRESS UPDATE
The PDU1032H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, T
OAX
,
is required before the address lines can change.
This time is given by the following relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the
AC
Characteristics
table. The
recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The
suggested
conditions are
those for which signals will propagate through the
unit without significant distortion. The
absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
A4-A0
T
AENS
ENB
T
ENIS
IN
TD
A
OUT
A
i-1
T
OAX
PW
IN
PW
OUT
T
DISO
T
AIS
A
i
T
DISH
Figure 1: Timing Diagram
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
PDU1032H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
SYMBOL
MIN
Total Programmable Delay
TD
T
Inherent Delay
TD
0
Disable to Output Low Delay
T
DISO
Address to Enable Setup Time
T
AENS
1.0
Address to Input Setup Time
T
AIS
3.6
Enable to Input Setup Time
T
ENIS
3.6
Output to Address Change
T
OAX
See Text
Disable Hold Time
T
DISH
See Text
Absolute
PER
IN
16
Input Period
Suggested
PER
IN
40
Recommended
PER
IN
200
Absolute
PW
IN
8
Input Pulse Width
Suggested
PW
IN
20
Recommended
PW
IN
100
* Greater for dash numbers larger than 5
TYP
31
5.5
1.7
UNITS
T
INC
ns*
ns
ns
ns
ns
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
EE
V
IN
T
STRG
T
LEAD
MIN
-7.0
V
EE
- 0.3
-55
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
MIN
-1.020
-1.950
-1.480
475
0.5
TYP
MAX
-0.735
-1.600
-1.070
UNITS
V
V
V
V
µA
µA
NOTES
V
IH
= MAX,50Ω to -2V
V
IL
= MIN, 50Ω to -2V
V
IH
= MAX
V
IL
= MIN
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
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