DATASHEET
ISL6745A
Improved Bridge Controller with Precision Dead Time Control
The
ISL6745A
is a low-cost, double-ended, voltage-mode
PWM controller designed for half-bridge and full-bridge
power supplies and line-regulated bus converters. It
provides precise control of switching frequency, adjustable
soft-start, and overcurrent shutdown. In addition, the
ISL6745A allows for accurate adjustment of MOSFET
non-overlap time (“dead time”) with dead times as low as
35ns, allowing power engineers to optimize the efficiency
of open-loop bus converters. The ISL6745A also includes a
control voltage input for closed-loop PWM and line voltage
feed-forward functions. The ISL6745A is identical to the
ISL6745, but is optimized for higher noise environments.
Low start-up and operating currents allow for easy biasing
in both AC/DC and DC/DC applications. This advanced
BiCMOS design also features adjustable switching
frequency up to 1MHz, 1A FET drivers, and very low
propagation delays for a fast response to overcurrent faults.
The ISL6745A is available in a space-saving 10 Ld MSOP
package and is assured to meet rated specifications across a
wide -40°C to +105°C temperature range.
FN6703
Rev.2.00
Aug 14, 2017
Features
• Precision duty cycle and dead time control
• 100µA start-up current
• Adjustable delayed overcurrent shutdown and restart
• Adjustable oscillator frequency up to 2MHz
• 1A MOSFET gate drivers
• Adjustable soft-start
• Internal over-temperature protection
• 35ns control to output propagation delay
• Small size and minimal external component count
• Input undervoltage protection
• Pb-free (RoHS compliant)
Applications
• Half-bridge converters
• Full-bridge converters
• Line-regulated bus converters
• AC/DC power supplies
• Telecom, datacom, and file server power
Related Literature
• For a full list of related documents, visit our website
•
ISL6745A
product page
FN6703 Rev.2.00
Aug 14, 2017
Page 1 of 13
1.
1.1
Overview
Internal Architecture
V
DDP
FL
I
DCH
= 55 x
I
RTD
FN6703 Rev.2.00
Aug 14, 2017
Page 2 of 13
ISL6745A
V
DD
V
BIAS
5.00V
UVLO
V
BIAS
Q
T
Q
PWM Toggle
V
BIAS
70µA
ON
OUTB
OUTA
+
-
BG
GND
Internal
OT Shutdown
130°C - 150°C
SS
V
BIAS
SS Clamp
R
TD
I
RTD
V
BIAS
160µA
ON
2.8V
-
+
Peak
S
Q
CLK
2.0V
-
+
4.0V
+
-
SS Charged
+
-
3.9V
15µA
S
Q
R Q
OC Latch
C
T
0.8V
-
+
Valley
R Q
Reset
Dominant
Q
50µs
Retriggerable
One Shot
Q
SS Low
+
-
SS
0.27V
Fault Latch
Set Dominant
S Q
R Q
FL
I
DCH
S Q
R Q
ON
PWM Latch
Set Dominant
V
BIAS
UV
4.65V
4.80V
-
+
BG
V
BIAS
CS
0.6V
+
-
OC Detect
PWM Comparator
V
BIA
S
C
T
15µA
+
-
-
1. Overview
V
ERR
0.8
SS
0.8
Figure 1. Internal Architecture
FN6703 Rev.2.00
Aug 14, 2017
Page 3 of 13
ISL6745A
1.2
VIN+
Typical Application - Telecom DC/DC Converter
Q1
C1
T1
CR1
+
+ VOUT
36V to 75V
(100V Max.)
T2
Q2
C2
CR2
L1
C10
RETURN
VIN-
CR3
CR4
U2
ISL2100A
1 VDD
2 HB
LO 8
VSS 7
LI 6
HI 5
C6
3 HO
4 HS
R1
U1
ISL6745
A
1 SS
VDD 10
C9
R6
R10
R7
C8
R11
U3
2 RTD VDDP 9
3 VERR OUTB 8
Q3
4 CS
5 CT
OUTA 7
GND 6
R4
C7
R8
R3
VR1
C2
R2
C3
C4
C5
VR2
R5
U4
TL431
R9
Figure 2. Typical Application
1. Overview
ISL6745A
1. Overview
1.3
Ordering Information
Part Number
(Notes
1, 2, 3)
Part Marking
6745A
Evaluation Board
Temp. Range
(°C)
-40 to +105
Package
(RoHS Compliant)
10 Ld MSOP
Pkg.
Dwg. #
M10.118
ISL6745AAUZ
ISL6745ALEVAL3Z
Notes:
1. Add “-T” suffix for 2.5k unit tape and reel option. Refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the product information page for
ISL6745A.
For more information on MSL, refer to
TB363.
1.4
Pin Configuration
ISL6745A
(10 Ld MSOP)
Top View
SS 1
RTD 2
VERR 3
CS 4
CT 5
10 VDD
9 VDDP
8 OUTB
7 OUTA
6 GND
FN6703 Rev.2.00
Aug 14, 2017
Page 4 of 13
ISL6745A
1. Overview
1.5
Pin Descriptions
Description
Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle during start-up, controls the overcurrent shutdown delay, and
the overcurrent and short-circuit hiccup restart period.
Oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The
current flowing through the resistor determines the magnitude of the discharge current. The discharge current is
nominally 55x this current. The PWM dead time is determined by the timing capacitor discharge duration.
Inverting input of the PWM comparator. The error voltage is applied to this pin to control the duty cycle. Increasing
the signal level increases the duty cycle. The node may be driven with an external error amplifier or an optocoupler.
Input to the overcurrent protection comparator. The overcurrent comparator threshold is set at 0.600V nominal. The
CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a
series input resistor may be required due to the delay between the internal clock and the external power switch.
Exceeding the overcurrent threshold will start a delayed shutdown sequence. When an overcurrent condition is
detected, the soft-start charge current source is disabled. The soft-start capacitor begins discharging through a 15µA
current source, and if it discharges to less than 3.9V (Sustained Overcurrent Threshold), a shutdown condition
occurs and the OUTA and OUTB outputs are forced low. When the soft-start voltage reaches 0.27V (Reset
Threshold) a soft-start cycle begins.
If the overcurrent condition ceases, and then an additional 50µs period elapses before the shutdown threshold is
reached, no shutdown occurs. The SS charging current is re-enabled and the soft-start voltage is allowed to recover.
The oscillator timing capacitor is connected between this pin and GND.
Reference and power ground for all functions on this device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended.
Alternate half cycle output stages. Each output is capable of 1A peak currents for driving power MOSFETs or
MOSFET drivers. Each output provides very low impedance to overshoot and undershoot.
VDDP is the separate collector supply to the gate drive. Having a separate VDDP pin helps isolate the analog
circuitry from the high power gate drive noise.
VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as
close to the VDD and GND pins as possible.
The total supply current, I
DD
, will be dependent on the load applied to outputs OUTA and OUTB. Total I
DD
current is
the sum of the quiescent current and the average output current. Knowing the operating frequency, f
SW
, and the
output loading capacitance charge, Q, per output, the average output current can be calculated from
(EQ. 1):
I
OUT
=
2
Q
f
SW
A
(EQ. 1)
Pin
Pin
Name Number
SS
1
RTD
2
VERR
CS
3
4
CT
GND
OUTA
OUTB
VDDP
VDD
5
6
7
8
9
10
FN6703 Rev.2.00
Aug 14, 2017
Page 5 of 13
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