PI3PCIE3422
3.3V, PCI Express® 3.0 2-Lane, (4-Channel), Differential Mux/Demux with Bypass
Features
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Description
Pericom semiconductor’s PI3PCIE3422 is an 8 to 4 channel
differential multiplexer/demultiplexer featuring 8-channel pass-
through. It supports two full PCIe® lanes at 8.0Gbps PCIe® 3.0
performance.
With the select control input low Port A connects to Port B, and
Port C connects to port D for an 8-channel differential pass-
though. When the select control input is high Port A connects
to Port D, and Port B and Port C are in a high-impedance state.
The mux/demux function is between Port A and Ports B or D as
determined by the select input control.
8 Differential Channel SPST switch with Mux/DeMux option
PCIe® 3.0 performance
Bi-directional operation
Low Bit-to-Bit Skew: 10ps (between ± signals)
Low Crosstalk: -50dB @ 4.0GHz (8Gbps)
Low Off Isolation: -21dB @4GHz
Low Insertion Loss: -1.8dB @ 4.0GHz (8Gbps)
Return Loss: -15dB @4GHz
V
DD
Operating Range: 3.3V ±10%
ESD Tolerance: 2kV HBM
Packaging (Pb-free & Green): 42-contact, TQFN (ZH42)
Truth Table
Function
Ax = Bx
Cx = Dx
Ax = Dx
B = C = Hi-Z
Ax, Bx, Cx, Dx = Hi-Z (disconnected)
SEL
L
H
x
OE#
0
0
1
Pin Diagram (Top-side view)
OE#
GND
VDD
A0+
A0-
C0+
C0-
A1+
VDD
41
42
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
B0+
B0-
D0+
D0-
B1+
B1-
D1+
D1-
VDD
B2+
B2-
D2+
D2-
B3+
B3-
D3+
D3-
Block Diagram
OE#
SEL
A0+
A0-
C0+
C0-
B0+
B0-
A1-
C1+
C1-
SEL
A2+
A2-
C2+
C2-
A3+
A3-
C3+
C3-
D0+
D0-
B1+
B1-
GND
A1+
A1-
C1+
C1-
D1+
D1-
B2+
B2-
A2+
A2-
C2+
C2-
19
20
VDD
18
21
GND
D2+
D2-
B3+
B3-
22
C3+
C3-
D3+
D3-
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GND
VDD
A3+
A3-
P-0.3
12/12/12
3.3V, PCI Express® 3.0 2-Lane, Differential Mux/Demux with Bypass
Pin Description
Pin #
1
2
5
6
10
11
14
15
38
37
34
33
29
28
25
24
3
4
7
8
12
13
16
17
36
35
32
31
27
26
23
22
41
9
18, 20, 30, 40, 42
19, 21, 39, Center Pad
PI3PCIE3422
Pin Name I/O
A0+
A0–
A1+
A1–
A2+
A2–
A3+
A3–
B0+
B0−
B1+
B1−
B2+
B2−
B3+
B3−
C0+
C0–
C1+
C1–
C2+
C2–
C3+
C3−
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
OE#
SEL
V
DD
GND
I
I
Pwr
Pwr
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Signal I/O, Channel 0, Port A
Signal I/O, Channel 1, Port A
Signal I/O, Channel 2, Port A
Signal I/O, Channel 3, Port A
Signal I/O, Channel 0, Port B
Signal I/O, Channel 1, Port B
Signal I/O, Channel 2, Port B
Signal I/O, Channel 3, Port B
Signal I/O, Channel 0, Port C
Signal I/O, Channel 1, Port C
Signal I/O, Channel 2, Port C
Signal I/O, Channel 3, Port C
Signal I/O, Channel 0, Port D
Signal I/O, Channel 1, Port D
Signal I/O, Channel 2, Port D
Signal I/O, Channel 3, Port D
Output Enable, active low. When OE# = 0 the device I/O is enabled. When OE#=1,
all I/O are high impedance
Operation mode Select
(when SEL=0: A→B, C→D, when SEL=1: A→D, B + C = Hi-Z)
3.3V ±10% Positive Supply Voltage
Power ground
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3.3V, PCI Express® 3.0 2-Lane, Differential Mux/Demux with Bypass
Maximum Ratings
PI3PCIE3422
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................................–65°C to +150°C
Supply Voltage to Ground Potential ................................–0.5V to +4.6V
Channel DC Input Voltage ................................................ –0.5V to 1.5V
DC Output Current ....................................................................... 120mA
Power Dissipation ........................................................................... 0.5W
SEL DC Input Voltage ....................................................... –0.5V to 4.6V
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Ex-
posure to absolute maximum rating conditions for extended
periods may affect reliability.
Electrical Characteristics
Recommended Operating Conditions
Symbol
V
DD
I
DD
T
CASE
Parameter
3.3V Power Supply
Total current from V
DD
3.3V supply
Case temperature range
for operation within spec.
SEL and OE# at OV or V
DD
-40
Conditions
Min
3.0
Typ
3.3
0.15
Max
3.6
1
85
Units
V
mA
Celsius
DC Electrical Characteristics for Switching over Operating Range
Parameters
V
IH
- SEL
V
IL
- SEL
V
IK
I
IH
I
IH
I
IL
R
ON
C
ON
I
OZ
Note:
1.
Typical values are at VDD = 3.3V, TA = 25°C ambient and maximum loading.
Description
Input HIGH Voltage, SEL input
Input LOW Voltage, SEL input
Clamp Diode Voltage
Input HIGH Current for OE#
and SEL
Input HIGH Current
Input LOW Current
On Channel Resistance
On Channel Capacitance
Output Current
Test Conditions
(1)
Guaranteed HIGH level
Guaranteed LOW level
V
DD
= Max., V
IN
= –18mA
V
DD
= Max., V
IN
= V
DD
V
DD
= Max., V
IN
= 1.5V
V
DD
= Max., V
IN
= GND
V
DD
= Min., V
IN
= 1.3V,
I
IN
= 40mA
V
DD
= 3.3V, V
IN
= 0
V
DD
= Max., V
IN
= 0V to 1.5V
Min
2
0
Typ(1)
Max
3.6
0.8
Units
V
–0.7
-10
-10
-10
8
2.5
-10
–1.2
10
+10
+10
15
Ohm
pF
+10
µA
µA
Switching Characteristics
Parameters
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
b-b
t
ch-ch
Description
Line Enable Time - SEL to A
N
, B
N
, C
N
, D
N
Line Disable Time - SEL to A
N
, B
N
, C
N
, D
N
Bit-to-bit skew within the same differential pair
Channel-to-channel skew
3
Test Conditions
Min.
0.5
0.5
Typ.
15
5
4
Max.
25
25
10
20
Units
ns
ps
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P-0.3
12/12/12
3.3V, PCI Express® 3.0 2-Lane, Differential Mux/Demux with Bypass
Dynamic Electrical Characteristics
Parameter
BW
Description
Bandwidth -3dB
f=1.25GHz
DDIL
Differential Insertion Loss
(V
IN
= -10dBm, DC = 0V)
f=2.5GHz
f=4.0GHz
f=5.0GHz
f=8.0GHz
DDIL
OFF
DDRL
Differential Off Isolation
Differential Return Loss
f= 4.0GHz
f= 0 to 1.25GHz
f= 1.25 to 2.5GHz
f= 2.5 to 4.0GHz
f= 0 to 2.8GHz
DDNEXT
Notes:
1.
Guaranteed by design. Typical values are at V DD = 3.3V , TA = 25°C ambient and maximum loading.
PI3PCIE3422
Test Conditions
Min.
Typ.
(1)
7
-0.9
-1.2
-1.7
-2.0
-5.0
-19
-16
-15
-15
-52
-50
-48
Max.
-1.0
-1.3
-1.8
-2.1
-5.1
Units
GHz
dB
dB
-15
-14
-14
dB
dB
Near End Crosstalk
f= 2.8 to 5.0GHz
f= 5.0 to 8.0GHz
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P-0.3
12/12/12
3.3V, PCI Express® 3.0 2-Lane, Differential Mux/Demux with Bypass
PI3PCIE3422
Differential Insertion Loss
Differential Return Loss
All trademarks are property of their respective owners.
13-0011
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P-0.3
12/12/12
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