Digital Inputs ............................................................. –0.3V to V
DIG
+0.3V
Maximum Junction Temperature .................................................. +165°C
Internal Power Dissipation ............................................................ 700mW
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
±0.9
"
±0.45
"
MINIMUM
SIGNAL-TO-
SPECIFIED
(NOISE + DISTORTION)
PACKAGE
TEMPERATURE
RATIO (DB)
PACKAGE-LEAD DESIGNATOR
(1)
RANGE
70
"
72
"
SO-20
"
"
"
DW
"
"
"
–40°C to +85°C
"
"
"
PRODUCT
ADS7808U
"
ADS7808UB
"
PACKAGE
MARKING
ADS7808U
"
ORDERING
NUMBER
ADS7808U
ADS7808U/1K
TRANSPORT
MEDIA, QUANTITY
Tube, 38
Tape and Reel, 1000
Tube, 38
Tape and Reel, 1000
ADS7808UB
ADS7808UB
"
ADS7808UB/1K
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At T
A
= –40°C to +85°C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.
ADS7808U
PARAMETER
RESOLUTION
ANALOG INPUT
Voltage Ranges
Impedance
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
(2)
Full Scale Error
(3,4)
Full Scale Error Drift
Full Scale Error
(3,4)
Full Scale Error Drift
Bipolar Zero Error
(3)
Bipolar Zero Error Drift
Unipolar Zero Error
(3)
CONDITIONS
MIN
TYP
MAX
12
±10V,
0V to 5V, etc. (See Table I)
See Table I
35
✻
✻
✻
±0.9
±0.9
Specified
0.1
±7
Ext. 2.5000V Ref
Ext. 2.5000V Ref
Bipolar Ranges
Bipolar Ranges
0V to 10V Range
0V to 4V Range
0V to 5V Range
Unipolar Ranges
1µF Capacitor to CAP
+4.75V < V
D
< +5.25V
±2
±2
±0.5
±0.5
±10
±5
±3
±3
✻
✻
±5
✻
✻
±2
✻
✻
✻
✻
✻
±0.5
✻
±0.25
±0.25
±0.45
±0.45
✻
✻
MIN
ADS7808UB
TYP
MAX
✻
UNITS
Bits
pF
µs
µs
kHz
LSB
(1)
LSB
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
mV
mV
ppm/°C
ms
LSB
5.7
Acquire and Convert
100
8
10
Unipolar Zero Error Drift
Recovery to Rated Accuracy
after Power Down
Power Supply Sensitivity
(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Full-Power Bandwidth
(6)
±2
1
f
IN
=
f
IN
=
f
IN
=
f
IN
=
45kHz
45kHz
45kHz
45kHz
80
70
70
90
–90
73
73
250
✻
–80
72
72
✻
✻
✻
✻
✻
✻
dB
(5)
dB
dB
dB
kHz
2
ADS7808
www.ti.com
SBAS018A
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= –40°C to +85°C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808U
PARAMETER
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
(7)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer)
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
V
IL
V
IH(8)
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Internal
(Output Only When
Transmitting Data)
External
(Can Run Continually)
V
OL
V
OH
Leakage Current
Output Capacitance
POWER SUPPLIES
Specified Performance
V
DIG
V
ANA
I
DIG
I
ANA
Power Dissipation: PWRD LOW
PWRD HIGH
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (
θ
JA
)
SO
✻
Specifications same as ADS7808U.
NOTES: (1) LSB means Least Significant Bit. For the
±10V
input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of
–Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and
includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale
±10V
input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum V
IH
level for the DATACLK
signal is 3V.
CONDITIONS
MIN
TYP
MAX
MIN
ADS7808UB
TYP
MAX
UNITS
FS Step
40
Sufficient to meet AC specs
2
150
✻
✻
✻
✻
✻
✻
✻
✻
✻
ns
ns
µs
ns
No Load
2.48
2.5
1
2.5
2.52
V
µA
V
µA
2.3
Ext. 2.5000V Ref
2.7
100
✻
✻
✻
–0.3
+2.0
V
IL
= 0V
V
IH
= 5V
+0.8
V
D
+0.3V
±10
±10
✻
✻
✻
✻
✻
✻
V
V
µA
µA
EXT/INT LOW
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
2.3
✻
MHz
EXT/INT HIGH
I
SINK
= 1.6mA
I
SOURCE
= 500µA
High-Z State,
V
OUT
= 0V to V
DIG
High-Z State
0.1
10
+0.4
✻
✻
✻
MHz
V
V
µA
pF
+4
±5
15
✻
✻
15
Must be
≤
V
ANA
+4.75
+4.75
+5
0.3
16
+5
+5.25
+5.25
✻
✻
✻
✻
✻
✻
✻
V
DIG
= V
ANA
= 5V, f
S
= 100kHz
50
100
✻
✻
✻
✻
✻
✻
V
mA
mA
✻
V
mW
µW
°C
°C
°C
–40
–55
–65
75
+85
+125
+150
✻
✻
✻
°CW
ADS7808
SBAS018A
www.ti.com
3
PIN ASSIGNMENTS
PIN #
1
2
3
4
5
6
7
8
9
NAME
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
DESCRIPTION
Analog Input. See Table I and Figure 4 for input range connections.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Analog Input. See Table I and Figure 4 for input range connections.
Analog Input. See Table I and Figure 4 for input range connections.
Reference Buffer Capacitor. 2.2µF Tantalum to ground.
Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2µF Tantalum capacitor.
Analog Ground.
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
Digital Ground.
Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
Chip Select. Internally OR’ed with R/C.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be
≤
V
ANA
.
10
11
12
13
DGND
SYNC
DATACLK
DATA
14
15
TAG
R/C
16
17
18
19
20
CS
BUSY
PWRD
V
ANA
V
DIG
PIN CONFIGURATION
ANALOG
INPUT
RANGE
±10V
±5V
±3.33
0V to 10V
0V to 5V
0V to 4V
CONNECT R1
IN
VIA 200Ω
TO
V
IN
AGND
V
IN
AGND
AGND
V
IN
CONNECT R2
IN
VIA 100Ω
CONNECT R3
IN
TO
TO
AGND
V
IN
V
IN
V
IN
AGND
AGND
CAP
CAP
CAP
AGND
V
IN
V
IN
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
1
2
3
4
5
6
7
8
9
ADS7808
20 V
DIG
19 V
ANA
18 PWRD
17 BUSY
16 CS
15 R/C
14 TAG
13 DATA
12 DATACLK
11 SYNC
IMPEDANCE
22.9kΩ
13.3kΩ
10.7kΩ
13.3kΩ
10.0kΩ
10.7kΩ
TABLE I. Input Range Connections. See Figure 4 for
complete information.
DGND 10
4
ADS7808
www.ti.com
SBAS018A
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
6
+ t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
DESCRIPTION
Convert Pulse Width
BUSY Delay
BUSY LOW
BUSY Delay after
End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
R/C LOW to DATACLK Delay
DATACLK Period
Data Valid to DATACLK
HIGH Delay
Data Valid after
DATACLK LOW Delay
External DATACLK Period
External DATACLK HIGH
External DATACLK LOW
DATACLK HIGH
Setup Time
R/C to CS
Setup Time
SYNC Delay After
DATACLK HIGH
Data Valid Delay
CS to Rising Edge Delay
Data Available after CS LOW
MIN
40
TYP MAX UNITS
4500
65
8
220
40
5.7
8
2
9
450
440
10
ns
ns
µs
ns
MODE Acquire
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
t
12
+ 5
ns
ns
35
55
ns
ns
ns
µs
CS, R/C
BUSY
t
2
t
1
t
3
t
4
t
5
Convert
t
6
Acquire
t
7
FIGURE 1. Basic Conversion Timing.
20
100
100
20
30
20
10
15
25
25
4.5
75
125
TABLE II. Conversion and Data Timing T
A
= –40°C to +85°C.
t
8
R/C
t
9
DATACLK
1
2
t
11
3
11
12
t
10
SDATA
t
2
t
3
BUSY
MSB Valid
Bit 10 Valid
Bit 9 Valid
Bit 1 Valid
LSB Valid
FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.)
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